Use hardcoded pagetable initially.
This pagetable is built into the binary, and maps device memory and enough RAM for the DT and image. It can later be replaced by a proper pagetable built in Rust. Using a hardcoded pagetable means we avoid making any memory access before enabling it, which avoids a bunch of cache issues. Bug: 223166344 Test: Ran unprotected VM under crosvm. Change-Id: I567e377ab93881aa357428f750b11be6b3aad034
This commit is contained in:
Andrew Walbran
parent
15068b023f
commit
267f6c1fcc
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@ -21,6 +21,7 @@ cc_binary {
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name: "pvmfw",
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srcs: [
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"entry.S",
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"idmap.S",
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],
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static_libs: [
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"libpvmfw",
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@ -19,6 +19,57 @@
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add \reg, \reg, :lo12:\sym
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.endm
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.macro mov_i, reg:req, imm:req
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movz \reg, :abs_g3:\imm
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movk \reg, :abs_g2_nc:\imm
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movk \reg, :abs_g1_nc:\imm
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movk \reg, :abs_g0_nc:\imm
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.endm
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.set .L_MAIR_DEV_nGnRE, 0x04
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.set .L_MAIR_MEM_WBWA, 0xff
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.set .Lmairval, .L_MAIR_DEV_nGnRE | (.L_MAIR_MEM_WBWA << 8)
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/* 4 KiB granule size for TTBR0_EL1. */
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.set .L_TCR_TG0_4KB, 0x0 << 14
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/* 4 KiB granule size for TTBR1_EL1. */
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.set .L_TCR_TG1_4KB, 0x2 << 30
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/* Disable translation table walk for TTBR1_EL1, generating a translation fault instead. */
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.set .L_TCR_EPD1, 0x1 << 23
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/* Translation table walks for TTBR0_EL1 are inner sharable. */
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.set .L_TCR_SH_INNER, 0x3 << 12
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/*
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* Translation table walks for TTBR0_EL1 are outer write-back read-allocate write-allocate
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* cacheable.
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*/
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.set .L_TCR_RGN_OWB, 0x1 << 10
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/*
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* Translation table walks for TTBR0_EL1 are inner write-back read-allocate write-allocate
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* cacheable.
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*/
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.set .L_TCR_RGN_IWB, 0x1 << 8
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/* Size offset for TTBR0_EL1 is 2**39 bytes (512 GiB). */
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.set .L_TCR_T0SZ_512, 64 - 39
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.set .Ltcrval, .L_TCR_TG0_4KB | .L_TCR_TG1_4KB | .L_TCR_EPD1 | .L_TCR_RGN_OWB
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.set .Ltcrval, .Ltcrval | .L_TCR_RGN_IWB | .L_TCR_SH_INNER | .L_TCR_T0SZ_512
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/* Stage 1 instruction access cacheability is unaffected. */
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.set .L_SCTLR_ELx_I, 0x1 << 12
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/* SP alignment fault if SP is not aligned to a 16 byte boundary. */
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.set .L_SCTLR_ELx_SA, 0x1 << 3
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/* Stage 1 data access cacheability is unaffected. */
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.set .L_SCTLR_ELx_C, 0x1 << 2
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/* EL0 and EL1 stage 1 MMU enabled. */
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.set .L_SCTLR_ELx_M, 0x1 << 0
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/* Privileged Access Never is unchanged on taking an exception to EL1. */
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.set .L_SCTLR_EL1_SPAN, 0x1 << 23
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/* SETEND instruction disabled at EL0 in aarch32 mode. */
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.set .L_SCTLR_EL1_SED, 0x1 << 8
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/* Various IT instructions are disabled at EL0 in aarch32 mode. */
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.set .L_SCTLR_EL1_ITD, 0x1 << 7
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.set .L_SCTLR_EL1_RES1, (0x1 << 11) | (0x1 << 20) | (0x1 << 22) | (0x1 << 28) | (0x1 << 29)
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.set .Lsctlrval, .L_SCTLR_ELx_M | .L_SCTLR_ELx_C | .L_SCTLR_ELx_SA | .L_SCTLR_EL1_ITD | .L_SCTLR_EL1_SED
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.set .Lsctlrval, .Lsctlrval | .L_SCTLR_ELx_I | .L_SCTLR_EL1_SPAN | .L_SCTLR_EL1_RES1
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/**
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* This is a generic entry point for an image. It carries out the operations
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* required to prepare the loaded image to be run. Specifically, it zeroes the
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@ -28,6 +79,41 @@
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.section .init.entry, "ax"
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.global entry
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entry:
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/* Enable MMU and caches. */
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/*
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* Load and apply the memory management configuration.
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*/
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adrp x1, idmap
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mov_i x2, .Lmairval
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mov_i x3, .Ltcrval
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mov_i x4, .Lsctlrval
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/* Copy the supported PA range into TCR_EL1.IPS. */
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mrs x6, id_aa64mmfr0_el1
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bfi x3, x6, #32, #4
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msr ttbr0_el1, x1
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msr mair_el1, x2
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msr tcr_el1, x3
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/*
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* Ensure everything before this point has completed, then invalidate any potentially stale
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* local TLB entries before they start being used.
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*/
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isb
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tlbi vmalle1
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ic iallu
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dsb nsh
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isb
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/*
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* Configure sctlr_el1 to enable MMU and cache and don't proceed until
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* this has completed.
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*/
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msr sctlr_el1, x4
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isb
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/* Disable trapping floating point access in EL1. */
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mrs x30, cpacr_el1
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orr x30, x30, #(0x3 << 20)
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@ -0,0 +1,48 @@
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/*
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* Copyright 2022 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* https://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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.set .L_TT_TYPE_BLOCK, 0x1
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.set .L_TT_TYPE_PAGE, 0x3
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.set .L_TT_TYPE_TABLE, 0x3
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/* Access flag. */
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.set .L_TT_AF, 0x1 << 10
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/* Not global. */
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.set .L_TT_NG, 0x1 << 11
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.set .L_TT_RO, 0x2 << 6
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.set .L_TT_XN, 0x3 << 53
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.set .L_TT_MT_DEV, 0x0 << 2 // MAIR #0 (DEV_nGnRE)
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.set .L_TT_MT_MEM, (0x1 << 2) | (0x3 << 8) // MAIR #1 (MEM_WBWA), inner shareable
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.set .L_BLOCK_RO, .L_TT_TYPE_BLOCK | .L_TT_MT_MEM | .L_TT_AF | .L_TT_RO | .L_TT_XN
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.set .L_BLOCK_DEV, .L_TT_TYPE_BLOCK | .L_TT_MT_DEV | .L_TT_AF | .L_TT_XN
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.set .L_BLOCK_MEM_XIP, .L_TT_TYPE_BLOCK | .L_TT_MT_MEM | .L_TT_AF | .L_TT_NG
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.section ".rodata.idmap", "a", %progbits
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.global idmap
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.align 12
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idmap:
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/* level 1 */
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.quad .L_BLOCK_DEV | 0x0 // 1 GB of device mappings
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.quad .L_BLOCK_DEV | 0x40000000 // Another 1 GB of device mapppings
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.quad .L_TT_TYPE_TABLE + 0f // up to 1 GB of DRAM
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.fill 509, 8, 0x0 // 509 GB of remaining VA space
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/* level 2 */
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0: .quad .L_BLOCK_RO | 0x80000000 // DT provided by VMM
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.quad .L_BLOCK_MEM_XIP | 0x80200000 // 2 MB of DRAM containing image
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.fill 510, 8, 0x0
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