From 267f6c1fcc0015ffe404e20031ecbf697acfa37f Mon Sep 17 00:00:00 2001 From: Andrew Walbran Date: Thu, 24 Mar 2022 11:26:36 +0000 Subject: [PATCH] Use hardcoded pagetable initially. This pagetable is built into the binary, and maps device memory and enough RAM for the DT and image. It can later be replaced by a proper pagetable built in Rust. Using a hardcoded pagetable means we avoid making any memory access before enabling it, which avoids a bunch of cache issues. Bug: 223166344 Test: Ran unprotected VM under crosvm. Change-Id: I567e377ab93881aa357428f750b11be6b3aad034 --- pvmfw/Android.bp | 1 + pvmfw/entry.S | 86 ++++++++++++++++++++++++++++++++++++++++++++++++ pvmfw/idmap.S | 48 +++++++++++++++++++++++++++ 3 files changed, 135 insertions(+) create mode 100644 pvmfw/idmap.S diff --git a/pvmfw/Android.bp b/pvmfw/Android.bp index d94334cb..7123da4c 100644 --- a/pvmfw/Android.bp +++ b/pvmfw/Android.bp @@ -21,6 +21,7 @@ cc_binary { name: "pvmfw", srcs: [ "entry.S", + "idmap.S", ], static_libs: [ "libpvmfw", diff --git a/pvmfw/entry.S b/pvmfw/entry.S index 25631cb0..787b4ffb 100644 --- a/pvmfw/entry.S +++ b/pvmfw/entry.S @@ -19,6 +19,57 @@ add \reg, \reg, :lo12:\sym .endm +.macro mov_i, reg:req, imm:req + movz \reg, :abs_g3:\imm + movk \reg, :abs_g2_nc:\imm + movk \reg, :abs_g1_nc:\imm + movk \reg, :abs_g0_nc:\imm +.endm + +.set .L_MAIR_DEV_nGnRE, 0x04 +.set .L_MAIR_MEM_WBWA, 0xff +.set .Lmairval, .L_MAIR_DEV_nGnRE | (.L_MAIR_MEM_WBWA << 8) + +/* 4 KiB granule size for TTBR0_EL1. */ +.set .L_TCR_TG0_4KB, 0x0 << 14 +/* 4 KiB granule size for TTBR1_EL1. */ +.set .L_TCR_TG1_4KB, 0x2 << 30 +/* Disable translation table walk for TTBR1_EL1, generating a translation fault instead. */ +.set .L_TCR_EPD1, 0x1 << 23 +/* Translation table walks for TTBR0_EL1 are inner sharable. */ +.set .L_TCR_SH_INNER, 0x3 << 12 +/* + * Translation table walks for TTBR0_EL1 are outer write-back read-allocate write-allocate + * cacheable. + */ +.set .L_TCR_RGN_OWB, 0x1 << 10 +/* + * Translation table walks for TTBR0_EL1 are inner write-back read-allocate write-allocate + * cacheable. + */ +.set .L_TCR_RGN_IWB, 0x1 << 8 +/* Size offset for TTBR0_EL1 is 2**39 bytes (512 GiB). */ +.set .L_TCR_T0SZ_512, 64 - 39 +.set .Ltcrval, .L_TCR_TG0_4KB | .L_TCR_TG1_4KB | .L_TCR_EPD1 | .L_TCR_RGN_OWB +.set .Ltcrval, .Ltcrval | .L_TCR_RGN_IWB | .L_TCR_SH_INNER | .L_TCR_T0SZ_512 + +/* Stage 1 instruction access cacheability is unaffected. */ +.set .L_SCTLR_ELx_I, 0x1 << 12 +/* SP alignment fault if SP is not aligned to a 16 byte boundary. */ +.set .L_SCTLR_ELx_SA, 0x1 << 3 +/* Stage 1 data access cacheability is unaffected. */ +.set .L_SCTLR_ELx_C, 0x1 << 2 +/* EL0 and EL1 stage 1 MMU enabled. */ +.set .L_SCTLR_ELx_M, 0x1 << 0 +/* Privileged Access Never is unchanged on taking an exception to EL1. */ +.set .L_SCTLR_EL1_SPAN, 0x1 << 23 +/* SETEND instruction disabled at EL0 in aarch32 mode. */ +.set .L_SCTLR_EL1_SED, 0x1 << 8 +/* Various IT instructions are disabled at EL0 in aarch32 mode. */ +.set .L_SCTLR_EL1_ITD, 0x1 << 7 +.set .L_SCTLR_EL1_RES1, (0x1 << 11) | (0x1 << 20) | (0x1 << 22) | (0x1 << 28) | (0x1 << 29) +.set .Lsctlrval, .L_SCTLR_ELx_M | .L_SCTLR_ELx_C | .L_SCTLR_ELx_SA | .L_SCTLR_EL1_ITD | .L_SCTLR_EL1_SED +.set .Lsctlrval, .Lsctlrval | .L_SCTLR_ELx_I | .L_SCTLR_EL1_SPAN | .L_SCTLR_EL1_RES1 /** * This is a generic entry point for an image. It carries out the operations * required to prepare the loaded image to be run. Specifically, it zeroes the @@ -28,6 +79,41 @@ .section .init.entry, "ax" .global entry entry: + /* Enable MMU and caches. */ + + /* + * Load and apply the memory management configuration. + */ + adrp x1, idmap + mov_i x2, .Lmairval + mov_i x3, .Ltcrval + mov_i x4, .Lsctlrval + + /* Copy the supported PA range into TCR_EL1.IPS. */ + mrs x6, id_aa64mmfr0_el1 + bfi x3, x6, #32, #4 + + msr ttbr0_el1, x1 + msr mair_el1, x2 + msr tcr_el1, x3 + + /* + * Ensure everything before this point has completed, then invalidate any potentially stale + * local TLB entries before they start being used. + */ + isb + tlbi vmalle1 + ic iallu + dsb nsh + isb + + /* + * Configure sctlr_el1 to enable MMU and cache and don't proceed until + * this has completed. + */ + msr sctlr_el1, x4 + isb + /* Disable trapping floating point access in EL1. */ mrs x30, cpacr_el1 orr x30, x30, #(0x3 << 20) diff --git a/pvmfw/idmap.S b/pvmfw/idmap.S new file mode 100644 index 00000000..f5050afc --- /dev/null +++ b/pvmfw/idmap.S @@ -0,0 +1,48 @@ +/* + * Copyright 2022 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * https://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +.set .L_TT_TYPE_BLOCK, 0x1 +.set .L_TT_TYPE_PAGE, 0x3 +.set .L_TT_TYPE_TABLE, 0x3 + +/* Access flag. */ +.set .L_TT_AF, 0x1 << 10 +/* Not global. */ +.set .L_TT_NG, 0x1 << 11 +.set .L_TT_RO, 0x2 << 6 +.set .L_TT_XN, 0x3 << 53 + +.set .L_TT_MT_DEV, 0x0 << 2 // MAIR #0 (DEV_nGnRE) +.set .L_TT_MT_MEM, (0x1 << 2) | (0x3 << 8) // MAIR #1 (MEM_WBWA), inner shareable + +.set .L_BLOCK_RO, .L_TT_TYPE_BLOCK | .L_TT_MT_MEM | .L_TT_AF | .L_TT_RO | .L_TT_XN +.set .L_BLOCK_DEV, .L_TT_TYPE_BLOCK | .L_TT_MT_DEV | .L_TT_AF | .L_TT_XN +.set .L_BLOCK_MEM_XIP, .L_TT_TYPE_BLOCK | .L_TT_MT_MEM | .L_TT_AF | .L_TT_NG + +.section ".rodata.idmap", "a", %progbits +.global idmap +.align 12 +idmap: + /* level 1 */ + .quad .L_BLOCK_DEV | 0x0 // 1 GB of device mappings + .quad .L_BLOCK_DEV | 0x40000000 // Another 1 GB of device mapppings + .quad .L_TT_TYPE_TABLE + 0f // up to 1 GB of DRAM + .fill 509, 8, 0x0 // 509 GB of remaining VA space + + /* level 2 */ +0: .quad .L_BLOCK_RO | 0x80000000 // DT provided by VMM + .quad .L_BLOCK_MEM_XIP | 0x80200000 // 2 MB of DRAM containing image + .fill 510, 8, 0x0