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dragonheart_kernel_oneplus_sm8150
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drivers/mtd: Import OnePlus Changes 

Signed-off-by: Cyber Knight <cyberknight755@gmail.com>
This commit is contained in:
Cyber Knight 2021-09-26 01:45:04 +08:00
parent 19171c2bc0
commit a15f54e3ca
No known key found for this signature in database
GPG Key ID: 23BD4CCD326E9D64
9 changed files with 36 additions and 113 deletions
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1
drivers/mtd/chips/cfi_cmdset_0002.c
View File

@ -726,6 +726,7 @@ static struct mtd_info *cfi_amdstd_setup(struct mtd_info *mtd)
kfree(mtd->eraseregions);
kfree(mtd);
kfree(cfi->cmdset_priv);
kfree(cfi->cfiq);
return NULL;
}

23
drivers/mtd/cmdlinepart.c
View File

@ -228,29 +228,12 @@ static int mtdpart_setup_real(char *s)
struct cmdline_mtd_partition *this_mtd;
struct mtd_partition *parts;
int mtd_id_len, num_parts;
char *p, *mtd_id, *semicol;
/*
* Replace the first ';' by a NULL char so strrchr can work
* properly.
*/
semicol = strchr(s, ';');
if (semicol)
*semicol = '\0';
char *p, *mtd_id;
mtd_id = s;
/*
* fetch <mtd-id>. We use strrchr to ignore all ':' that could
* be present in the MTD name, only the last one is interpreted
* as an <mtd-id>/<part-definition> separator.
*/
p = strrchr(s, ':');
/* Restore the ';' now. */
if (semicol)
*semicol = ';';
/* fetch <mtd-id> */
p = strchr(s, ':');
if (!p) {
pr_err("no mtd-id\n");
return -EINVAL;

35
drivers/mtd/lpddr/lpddr2_nvm.c
View File

@ -408,17 +408,6 @@ static int lpddr2_nvm_lock(struct mtd_info *mtd, loff_t start_add,
return lpddr2_nvm_do_block_op(mtd, start_add, len, LPDDR2_NVM_LOCK);
}
static const struct mtd_info lpddr2_nvm_mtd_info = {
.type = MTD_RAM,
.writesize = 1,
.flags = (MTD_CAP_NVRAM | MTD_POWERUP_LOCK),
._read = lpddr2_nvm_read,
._write = lpddr2_nvm_write,
._erase = lpddr2_nvm_erase,
._unlock = lpddr2_nvm_unlock,
._lock = lpddr2_nvm_lock,
};
/*
* lpddr2_nvm driver probe method
*/
@ -459,7 +448,6 @@ static int lpddr2_nvm_probe(struct platform_device *pdev)
.pfow_base = OW_BASE_ADDRESS,
.fldrv_priv = pcm_data,
};
if (IS_ERR(map->virt))
return PTR_ERR(map->virt);
@ -471,13 +459,22 @@ static int lpddr2_nvm_probe(struct platform_device *pdev)
return PTR_ERR(pcm_data->ctl_regs);
/* Populate mtd_info data structure */
*mtd = lpddr2_nvm_mtd_info;
mtd->dev.parent = &pdev->dev;
mtd->name = pdev->dev.init_name;
mtd->priv = map;
mtd->size = resource_size(add_range);
mtd->erasesize = ERASE_BLOCKSIZE * pcm_data->bus_width;
mtd->writebufsize = WRITE_BUFFSIZE * pcm_data->bus_width;
*mtd = (struct mtd_info) {
.dev = { .parent = &pdev->dev },
.name = pdev->dev.init_name,
.type = MTD_RAM,
.priv = map,
.size = resource_size(add_range),
.erasesize = ERASE_BLOCKSIZE * pcm_data->bus_width,
.writesize = 1,
.writebufsize = WRITE_BUFFSIZE * pcm_data->bus_width,
.flags = (MTD_CAP_NVRAM | MTD_POWERUP_LOCK),
._read = lpddr2_nvm_read,
._write = lpddr2_nvm_write,
._erase = lpddr2_nvm_erase,
._unlock = lpddr2_nvm_unlock,
._lock = lpddr2_nvm_lock,
};
/* Verify the presence of the device looking for PFOW string */
if (!lpddr2_nvm_pfow_present(map)) {

56
drivers/mtd/mtdchar.c
View File

@ -373,6 +373,9 @@ static int mtdchar_writeoob(struct file *file, struct mtd_info *mtd,
uint32_t retlen;
int ret = 0;
if (!(file->f_mode & FMODE_WRITE))
return -EPERM;
if (length > 4096)
return -EINVAL;
@ -679,48 +682,6 @@ static int mtdchar_ioctl(struct file *file, u_int cmd, u_long arg)
return -EFAULT;
}
/*
* Check the file mode to require "dangerous" commands to have write
* permissions.
*/
switch (cmd) {
/* "safe" commands */
case MEMGETREGIONCOUNT:
case MEMGETREGIONINFO:
case MEMGETINFO:
case MEMREADOOB:
case MEMREADOOB64:
case MEMLOCK:
case MEMUNLOCK:
case MEMISLOCKED:
case MEMGETOOBSEL:
case MEMGETBADBLOCK:
case MEMSETBADBLOCK:
case OTPSELECT:
case OTPGETREGIONCOUNT:
case OTPGETREGIONINFO:
case OTPLOCK:
case ECCGETLAYOUT:
case ECCGETSTATS:
case MTDFILEMODE:
case BLKPG:
case BLKRRPART:
break;
/* "dangerous" commands */
case MEMERASE:
case MEMERASE64:
case MEMWRITEOOB:
case MEMWRITEOOB64:
case MEMWRITE:
if (!(file->f_mode & FMODE_WRITE))
return -EPERM;
break;
default:
return -ENOTTY;
}
switch (cmd) {
case MEMGETREGIONCOUNT:
if (copy_to_user(argp, &(mtd->numeraseregions), sizeof(int)))
@ -768,6 +729,9 @@ static int mtdchar_ioctl(struct file *file, u_int cmd, u_long arg)
{
struct erase_info *erase;
if(!(file->f_mode & FMODE_WRITE))
return -EPERM;
erase=kzalloc(sizeof(struct erase_info),GFP_KERNEL);
if (!erase)
ret = -ENOMEM;
@ -1091,6 +1055,9 @@ static int mtdchar_ioctl(struct file *file, u_int cmd, u_long arg)
ret = 0;
break;
}
default:
ret = -ENOTTY;
}
return ret;
@ -1134,11 +1101,6 @@ static long mtdchar_compat_ioctl(struct file *file, unsigned int cmd,
struct mtd_oob_buf32 buf;
struct mtd_oob_buf32 __user *buf_user = argp;
if (!(file->f_mode & FMODE_WRITE)) {
ret = -EPERM;
break;
}
if (copy_from_user(&buf, argp, sizeof(buf)))
ret = -EFAULT;
else

11
drivers/mtd/mtdoops.c
View File

@ -313,13 +313,12 @@ static void mtdoops_do_dump(struct kmsg_dumper *dumper,
kmsg_dump_get_buffer(dumper, true, cxt->oops_buf + MTDOOPS_HEADER_SIZE,
record_size - MTDOOPS_HEADER_SIZE, NULL);
if (reason != KMSG_DUMP_OOPS) {
/* Panics must be written immediately */
/* Panics must be written immediately */
if (reason != KMSG_DUMP_OOPS)
mtdoops_write(cxt, 1);
} else {
/* For other cases, schedule work to write it "nicely" */
schedule_work(&cxt->work_write);
}
/* For other cases, schedule work to write it "nicely" */
schedule_work(&cxt->work_write);
}
static void mtdoops_notify_add(struct mtd_info *mtd)

1
drivers/mtd/nand/omap_elm.c
View File

@ -421,7 +421,6 @@ static int elm_probe(struct platform_device *pdev)
pm_runtime_enable(&pdev->dev);
if (pm_runtime_get_sync(&pdev->dev) < 0) {
ret = -EINVAL;
pm_runtime_put_sync(&pdev->dev);
pm_runtime_disable(&pdev->dev);
dev_err(&pdev->dev, "can't enable clock\n");
return ret;

7
drivers/mtd/nand/qcom_nandc.c
View File

@ -435,13 +435,11 @@ struct qcom_nand_host {
* among different NAND controllers.
* @ecc_modes - ecc mode for NAND
* @is_bam - whether NAND controller is using BAM
* @is_qpic - whether NAND CTRL is part of qpic IP
* @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset
*/
struct qcom_nandc_props {
u32 ecc_modes;
bool is_bam;
bool is_qpic;
u32 dev_cmd_reg_start;
};
@ -2510,8 +2508,7 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
u32 nand_ctrl;
/* kill onenand */
if (!nandc->props->is_qpic)
nandc_write(nandc, SFLASHC_BURST_CFG, 0);
nandc_write(nandc, SFLASHC_BURST_CFG, 0);
nandc_write(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD),
NAND_DEV_CMD_VLD_VAL);
@ -2782,14 +2779,12 @@ static const struct qcom_nandc_props ipq806x_nandc_props = {
static const struct qcom_nandc_props ipq4019_nandc_props = {
.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
.is_bam = true,
.is_qpic = true,
.dev_cmd_reg_start = 0x0,
};
static const struct qcom_nandc_props ipq8074_nandc_props = {
.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
.is_bam = true,
.is_qpic = true,
.dev_cmd_reg_start = 0x7000,
};

2
drivers/mtd/nand/sunxi_nand.c
View File

@ -2125,7 +2125,7 @@ static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
ret = mtd_device_register(mtd, NULL, 0);
if (ret) {
dev_err(dev, "failed to register mtd device: %d\n", ret);
nand_cleanup(nand);
nand_release(nand);
return ret;
}

13
drivers/mtd/ubi/wl.c
View File

@ -1732,19 +1732,6 @@ int ubi_thread(void *u)
!ubi->thread_enabled || ubi_dbg_is_bgt_disabled(ubi)) {
set_current_state(TASK_INTERRUPTIBLE);
spin_unlock(&ubi->wl_lock);
/*
* Check kthread_should_stop() after we set the task
* state to guarantee that we either see the stop bit
* and exit or the task state is reset to runnable such
* that it's not scheduled out indefinitely and detects
* the stop bit at kthread_should_stop().
*/
if (kthread_should_stop()) {
set_current_state(TASK_RUNNING);
break;
}
schedule();
continue;
}