585 lines
18 KiB
C
585 lines
18 KiB
C
/* $NetBSD: db_disasm.c,v 1.19 2007/02/28 04:21:53 thorpej Exp $ */
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/*-
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* Copyright (c) 1991, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Ralph Campbell.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)kadb.c 8.1 (Berkeley) 6/10/93
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*/
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#include <stdarg.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <sys/cdefs.h>
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#include <sys/types.h>
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#include <android/log.h>
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#include "mips_opcode.h"
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#define __unused __attribute__((__unused__))
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static char *sprintf_buffer;
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static int sprintf_buf_len;
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typedef uint64_t db_addr_t;
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static void db_printf(const char* fmt, ...);
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static const char * const op_name[64] = {
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/* 0 */ "spec", "bcond", "j", "jal", "beq", "bne", "blez", "bgtz",
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/* 8 */ "pop10", "addiu", "slti", "sltiu", "andi", "ori", "xori", "aui",
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/*16 */ "cop0", "cop1", "cop2", "?", "?", "?", "pop26", "pop27",
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/*24 */ "pop30", "daddiu", "?", "?", "?", "daui", "msa", "op37",
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/*32 */ "lb", "lh", "?", "lw", "lbu", "lhu", "?", "lwu",
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/*40 */ "sb", "sh", "?", "sw", "?", "?", "?", "?",
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/*48 */ "?", "lwc1", "bc", "?", "?", "ldc1", "pop66", "ld",
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/*56 */ "?", "swc1", "balc", "pcrel", "?", "sdc1", "pop76", "sd"
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};
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static const char * const spec_name[64] = {
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/* 0 */ "sll", "?", "srl", "sra", "sllv", "?", "srlv", "srav",
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/* 8 */ "?", "jalr", "?", "?", "syscall", "break", "sdbpp", "sync",
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/*16 */ "clz", "clo", "dclz", "dclo", "dsllv", "dlsa", "dsrlv", "dsrav",
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/*24 */ "sop30", "sop31", "sop32", "sop33", "sop34", "sop35", "sop36", "sop37",
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/*32 */ "add", "addu", "sub", "subu", "and", "or", "xor", "nor",
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/*40 */ "?", "?", "slt", "sltu", "dadd", "daddu", "dsub", "dsubu",
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/*48 */ "tge", "tgeu", "tlt", "tltu", "teq", "seleqz", "tne", "selnez",
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/*56 */ "dsll", "?", "dsrl", "dsra", "dsll32", "?", "dsrl32", "dsra32"
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};
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static const char * const bcond_name[32] = {
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/* 0 */ "bltz", "bgez", "?", "?", "?", "?", "dahi", "?",
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/* 8 */ "?", "?", "?", "?", "?", "?", "?", "?",
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/*16 */ "nal", "bal", "?", "?", "?", "?", "?", "sigrie",
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/*24 */ "?", "?", "?", "?", "?", "?", "dati", "synci",
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};
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static const char * const cop1_name[64] = {
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/* 0 */ "fadd", "fsub", "fmpy", "fdiv", "fsqrt","fabs", "fmov", "fneg",
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/* 8 */ "fop08","fop09","fop0a","fop0b","fop0c","fop0d","fop0e","fop0f",
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/*16 */ "fop10","fop11","fop12","fop13","fop14","fop15","fop16","fop17",
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/*24 */ "fop18","fop19","fop1a","fop1b","fop1c","fop1d","fop1e","fop1f",
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/*32 */ "fcvts","fcvtd","fcvte","fop23","fcvtw","fop25","fop26","fop27",
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/*40 */ "fop28","fop29","fop2a","fop2b","fop2c","fop2d","fop2e","fop2f",
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/*48 */ "fcmp.f","fcmp.un","fcmp.eq","fcmp.ueq","fcmp.olt","fcmp.ult",
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"fcmp.ole","fcmp.ule",
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/*56 */ "fcmp.sf","fcmp.ngle","fcmp.seq","fcmp.ngl","fcmp.lt","fcmp.nge",
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"fcmp.le","fcmp.ngt"
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};
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static const char * const fmt_name[16] = {
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"s", "d", "e", "fmt3",
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"w", "fmt5", "fmt6", "fmt7",
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"fmt8", "fmt9", "fmta", "fmtb",
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"fmtc", "fmtd", "fmte", "fmtf"
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};
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static char * const mips_reg_name[32] = {
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"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
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"a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
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"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
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"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
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};
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static char * alt_arm_reg_name[32] = { // hacked names for comparison with ARM code
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"zero", "at", "r0", "r1", "r2", "r3", "r4", "r5",
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"r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13",
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"r14", "r15", "at2", "cmp", "s4", "s5", "s6", "s7",
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"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
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};
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static char * const * reg_name = &mips_reg_name[0];
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static const char * const c0_opname[64] = {
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"c0op00","tlbr", "tlbwi", "c0op03","c0op04","c0op05","tlbwr", "c0op07",
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"tlbp", "c0op11","c0op12","c0op13","c0op14","c0op15","c0op16","c0op17",
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"rfe", "c0op21","c0op22","c0op23","c0op24","c0op25","c0op26","c0op27",
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"eret", "c0op31","c0op32","c0op33","c0op34","c0op35","c0op36","c0op37",
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"c0op40","c0op41","c0op42","c0op43","c0op44","c0op45","c0op46","c0op47",
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"c0op50","c0op51","c0op52","c0op53","c0op54","c0op55","c0op56","c0op57",
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"c0op60","c0op61","c0op62","c0op63","c0op64","c0op65","c0op66","c0op67",
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"c0op70","c0op71","c0op72","c0op73","c0op74","c0op75","c0op77","c0op77",
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};
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static const char * const c0_reg[32] = {
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"index", "random", "tlblo0", "tlblo1",
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"context", "pagemask", "wired", "cp0r7",
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"badvaddr", "count", "tlbhi", "compare",
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"status", "cause", "epc", "prid",
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"config", "lladdr", "watchlo", "watchhi",
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"xcontext", "cp0r21", "cp0r22", "debug",
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"depc", "perfcnt", "ecc", "cacheerr",
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"taglo", "taghi", "errepc", "desave"
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};
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static void print_addr(db_addr_t);
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db_addr_t mips_disassem(db_addr_t loc, char *di_buffer, int alt_dis_format);
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/*
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* Disassemble instruction 'insn' nominally at 'loc'.
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* 'loc' may in fact contain a breakpoint instruction.
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*/
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static db_addr_t
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db_disasm_insn(int insn, db_addr_t loc, bool altfmt __unused)
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{
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bool bdslot = false;
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InstFmt i;
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i.word = insn;
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switch (i.JType.op) {
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case OP_SPECIAL:
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if (i.word == 0) {
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db_printf("nop");
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break;
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}
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if (i.word == 0x0080) {
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db_printf("NIY");
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break;
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}
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if (i.word == 0x00c0) {
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db_printf("NOT IMPL");
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break;
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}
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/* Special cases --------------------------------------------------
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* "addu" is a "move" only in 32-bit mode. What's the correct
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* answer - never decode addu/daddu as "move"?
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*/
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if ( (i.RType.func == OP_ADDU && i.RType.rt == 0) ||
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(i.RType.func == OP_OR && i.RType.rt == 0) ) {
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db_printf("move\t%s,%s",
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reg_name[i.RType.rd],
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reg_name[i.RType.rs]);
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break;
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}
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if (i.RType.func == OP_SRL && (i.RType.rs & 1) == 1) {
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db_printf("rotr\t%s,%s,%d", reg_name[i.RType.rd],
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reg_name[i.RType.rt], i.RType.shamt);
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break;
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}
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if (i.RType.func == OP_SRLV && (i.RType.shamt & 1) == 1) {
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db_printf("rotrv\t%s,%s,%s", reg_name[i.RType.rd],
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reg_name[i.RType.rt], reg_name[i.RType.rs]);
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break;
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}
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if (i.RType.func == OP_SOP30) {
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if (i.RType.shamt == OP_MUL) {
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db_printf("mul");
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} else if (i.RType.shamt == OP_MUH) {
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db_printf("muh");
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}
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db_printf("\t%s,%s,%s", reg_name[i.RType.rd],
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reg_name[i.RType.rs], reg_name[i.RType.rt]);
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break;
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}
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if (i.RType.func == OP_SOP31) {
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if (i.RType.shamt == OP_MUL) {
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db_printf("mulu");
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} else if (i.RType.shamt == OP_MUH) {
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db_printf("muhu");
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}
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db_printf("\t%s,%s,%s", reg_name[i.RType.rd],
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reg_name[i.RType.rs], reg_name[i.RType.rt]);
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break;
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}
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if (i.RType.func == OP_JALR && i.RType.rd == 0) {
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db_printf("jr\t%s", reg_name[i.RType.rs]);
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bdslot = true;
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break;
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}
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db_printf("%s", spec_name[i.RType.func]);
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switch (i.RType.func) {
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case OP_SLL:
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case OP_SRL:
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case OP_SRA:
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case OP_DSLL:
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case OP_DSRL:
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case OP_DSRA:
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case OP_DSLL32:
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case OP_DSRL32:
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case OP_DSRA32:
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db_printf("\t%s,%s,%d",
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reg_name[i.RType.rd],
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reg_name[i.RType.rt],
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i.RType.shamt);
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break;
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case OP_SLLV:
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case OP_SRLV:
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case OP_SRAV:
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case OP_DSLLV:
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case OP_DSRLV:
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case OP_DSRAV:
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db_printf("\t%s,%s,%s",
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reg_name[i.RType.rd],
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reg_name[i.RType.rt],
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reg_name[i.RType.rs]);
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break;
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case OP_CLZ:
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case OP_CLO:
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case OP_DCLZ:
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case OP_DCLO:
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db_printf("\t%s,%s",
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reg_name[i.RType.rd],
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reg_name[i.RType.rs]);
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break;
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case OP_JALR:
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db_printf("\t");
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if (i.RType.rd != 31) {
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db_printf("%s,", reg_name[i.RType.rd]);
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}
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db_printf("%s", reg_name[i.RType.rs]);
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bdslot = true;
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break;
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case OP_SYSCALL:
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case OP_SYNC:
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break;
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case OP_BREAK:
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db_printf("\t%d", (i.RType.rs << 5) | i.RType.rt);
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break;
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default:
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db_printf("\t%s,%s,%s",
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reg_name[i.RType.rd],
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reg_name[i.RType.rs],
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reg_name[i.RType.rt]);
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}
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break;
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case OP_SPECIAL3:
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if (i.RType.func == OP_EXT)
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db_printf("ext\t%s,%s,%d,%d",
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reg_name[i.RType.rt],
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reg_name[i.RType.rs],
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i.RType.shamt,
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i.RType.rd+1);
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else if (i.RType.func == OP_DEXT)
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db_printf("dext\t%s,%s,%d,%d",
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reg_name[i.RType.rt],
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reg_name[i.RType.rs],
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i.RType.shamt,
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i.RType.rd+1);
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else if (i.RType.func == OP_DEXTM)
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db_printf("dextm\t%s,%s,%d,%d",
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reg_name[i.RType.rt],
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reg_name[i.RType.rs],
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i.RType.shamt,
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i.RType.rd+33);
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else if (i.RType.func == OP_DEXTU)
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db_printf("dextu\t%s,%s,%d,%d",
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reg_name[i.RType.rt],
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reg_name[i.RType.rs],
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i.RType.shamt+32,
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i.RType.rd+1);
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else if (i.RType.func == OP_INS)
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db_printf("ins\t%s,%s,%d,%d",
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reg_name[i.RType.rt],
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reg_name[i.RType.rs],
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i.RType.shamt,
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i.RType.rd-i.RType.shamt+1);
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else if (i.RType.func == OP_DINS)
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db_printf("dins\t%s,%s,%d,%d",
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reg_name[i.RType.rt],
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reg_name[i.RType.rs],
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i.RType.shamt,
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i.RType.rd-i.RType.shamt+1);
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else if (i.RType.func == OP_DINSM)
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db_printf("dinsm\t%s,%s,%d,%d",
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reg_name[i.RType.rt],
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reg_name[i.RType.rs],
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i.RType.shamt,
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i.RType.rd-i.RType.shamt+33);
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else if (i.RType.func == OP_DINSU)
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db_printf("dinsu\t%s,%s,%d,%d",
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reg_name[i.RType.rt],
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reg_name[i.RType.rs],
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i.RType.shamt+32,
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i.RType.rd-i.RType.shamt+1);
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else if (i.RType.func == OP_BSHFL && i.RType.shamt == OP_WSBH)
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db_printf("wsbh\t%s,%s",
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reg_name[i.RType.rd],
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reg_name[i.RType.rt]);
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else if (i.RType.func == OP_BSHFL && i.RType.shamt == OP_SEB)
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db_printf("seb\t%s,%s",
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reg_name[i.RType.rd],
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reg_name[i.RType.rt]);
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else if (i.RType.func == OP_BSHFL && i.RType.shamt == OP_SEH)
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db_printf("seh\t%s,%s",
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reg_name[i.RType.rd],
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reg_name[i.RType.rt]);
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else if (i.RType.func == OP_RDHWR)
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db_printf("rdhwr\t%s,%s",
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reg_name[i.RType.rd],
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reg_name[i.RType.rt]);
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else
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db_printf("Unknown");
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break;
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case OP_BCOND:
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db_printf("%s\t%s,", bcond_name[i.IType.rt],
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reg_name[i.IType.rs]);
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goto pr_displ;
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case OP_BLEZ:
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case OP_BGTZ:
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db_printf("%s\t%s,", op_name[i.IType.op],
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reg_name[i.IType.rs]);
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goto pr_displ;
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case OP_BEQ:
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if (i.IType.rs == 0 && i.IType.rt == 0) {
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db_printf("b\t");
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goto pr_displ;
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}
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/* FALLTHROUGH */
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case OP_BNE:
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db_printf("%s\t%s,%s,", op_name[i.IType.op],
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reg_name[i.IType.rs],
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reg_name[i.IType.rt]);
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pr_displ:
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print_addr(loc + 4 + ((short)i.IType.imm << 2));
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bdslot = true;
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break;
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case OP_COP0:
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switch (i.RType.rs) {
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case OP_BCx:
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case OP_BCy:
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db_printf("bc0%c\t",
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"ft"[i.RType.rt & COPz_BC_TF_MASK]);
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goto pr_displ;
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case OP_MT:
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db_printf("mtc0\t%s,%s",
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reg_name[i.RType.rt],
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c0_reg[i.RType.rd]);
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break;
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case OP_DMT:
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db_printf("dmtc0\t%s,%s",
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reg_name[i.RType.rt],
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c0_reg[i.RType.rd]);
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break;
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case OP_MF:
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db_printf("mfc0\t%s,%s",
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reg_name[i.RType.rt],
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c0_reg[i.RType.rd]);
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break;
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case OP_DMF:
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db_printf("dmfc0\t%s,%s",
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reg_name[i.RType.rt],
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c0_reg[i.RType.rd]);
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break;
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|
|
|
default:
|
|
db_printf("%s", c0_opname[i.FRType.func]);
|
|
}
|
|
break;
|
|
|
|
case OP_COP1:
|
|
switch (i.RType.rs) {
|
|
case OP_BCx:
|
|
case OP_BCy:
|
|
db_printf("bc1%c\t",
|
|
"ft"[i.RType.rt & COPz_BC_TF_MASK]);
|
|
goto pr_displ;
|
|
|
|
case OP_MT:
|
|
db_printf("mtc1\t%s,f%d",
|
|
reg_name[i.RType.rt],
|
|
i.RType.rd);
|
|
break;
|
|
|
|
case OP_MF:
|
|
db_printf("mfc1\t%s,f%d",
|
|
reg_name[i.RType.rt],
|
|
i.RType.rd);
|
|
break;
|
|
|
|
case OP_CT:
|
|
db_printf("ctc1\t%s,f%d",
|
|
reg_name[i.RType.rt],
|
|
i.RType.rd);
|
|
break;
|
|
|
|
case OP_CF:
|
|
db_printf("cfc1\t%s,f%d",
|
|
reg_name[i.RType.rt],
|
|
i.RType.rd);
|
|
break;
|
|
|
|
default:
|
|
db_printf("%s.%s\tf%d,f%d,f%d",
|
|
cop1_name[i.FRType.func],
|
|
fmt_name[i.FRType.fmt],
|
|
i.FRType.fd, i.FRType.fs, i.FRType.ft);
|
|
}
|
|
break;
|
|
|
|
case OP_J:
|
|
case OP_JAL:
|
|
db_printf("%s\t", op_name[i.JType.op]);
|
|
print_addr((loc & 0xFFFFFFFFF0000000) | (i.JType.target << 2));
|
|
bdslot = true;
|
|
break;
|
|
|
|
case OP_LWC1:
|
|
case OP_SWC1:
|
|
db_printf("%s\tf%d,", op_name[i.IType.op],
|
|
i.IType.rt);
|
|
goto loadstore;
|
|
|
|
case OP_LB:
|
|
case OP_LH:
|
|
case OP_LW:
|
|
case OP_LD:
|
|
case OP_LBU:
|
|
case OP_LHU:
|
|
case OP_LWU:
|
|
case OP_SB:
|
|
case OP_SH:
|
|
case OP_SW:
|
|
case OP_SD:
|
|
db_printf("%s\t%s,", op_name[i.IType.op],
|
|
reg_name[i.IType.rt]);
|
|
loadstore:
|
|
db_printf("%d(%s)", (short)i.IType.imm,
|
|
reg_name[i.IType.rs]);
|
|
break;
|
|
|
|
case OP_ORI:
|
|
case OP_XORI:
|
|
if (i.IType.rs == 0) {
|
|
db_printf("li\t%s,0x%x",
|
|
reg_name[i.IType.rt],
|
|
i.IType.imm);
|
|
break;
|
|
}
|
|
/* FALLTHROUGH */
|
|
case OP_ANDI:
|
|
db_printf("%s\t%s,%s,0x%x", op_name[i.IType.op],
|
|
reg_name[i.IType.rt],
|
|
reg_name[i.IType.rs],
|
|
i.IType.imm);
|
|
break;
|
|
|
|
case OP_AUI:
|
|
if (i.IType.rs == 0) {
|
|
db_printf("lui\t%s,0x%x", reg_name[i.IType.rt],
|
|
i.IType.imm);
|
|
} else {
|
|
db_printf("%s\t%s,%s,%d", op_name[i.IType.op],
|
|
reg_name[i.IType.rt], reg_name[i.IType.rs],
|
|
(short)i.IType.imm);
|
|
}
|
|
break;
|
|
|
|
case OP_ADDIU:
|
|
case OP_DADDIU:
|
|
if (i.IType.rs == 0) {
|
|
db_printf("li\t%s,%d",
|
|
reg_name[i.IType.rt],
|
|
(short)i.IType.imm);
|
|
break;
|
|
}
|
|
/* FALLTHROUGH */
|
|
default:
|
|
db_printf("%s\t%s,%s,%d", op_name[i.IType.op],
|
|
reg_name[i.IType.rt],
|
|
reg_name[i.IType.rs],
|
|
(short)i.IType.imm);
|
|
}
|
|
// db_printf("\n");
|
|
// if (bdslot) {
|
|
// db_printf(" bd: ");
|
|
// mips_disassem(loc+4);
|
|
// return (loc + 8);
|
|
// }
|
|
return (loc + 4);
|
|
}
|
|
|
|
static void
|
|
print_addr(db_addr_t loc)
|
|
{
|
|
db_printf("0x%08lx", loc);
|
|
}
|
|
|
|
static void db_printf(const char* fmt, ...)
|
|
{
|
|
int cnt;
|
|
va_list argp;
|
|
va_start(argp, fmt);
|
|
if (sprintf_buffer) {
|
|
cnt = vsnprintf(sprintf_buffer, sprintf_buf_len, fmt, argp);
|
|
sprintf_buffer += cnt;
|
|
sprintf_buf_len -= cnt;
|
|
} else {
|
|
vprintf(fmt, argp);
|
|
}
|
|
va_end(argp);
|
|
}
|
|
|
|
/*
|
|
* Disassemble instruction at 'loc'.
|
|
* Return address of start of next instruction.
|
|
* Since this function is used by 'examine' and by 'step'
|
|
* "next instruction" does NOT mean the next instruction to
|
|
* be executed but the 'linear' next instruction.
|
|
*/
|
|
db_addr_t
|
|
mips_disassem(db_addr_t loc, char *di_buffer, int alt_dis_format)
|
|
{
|
|
u_int32_t instr;
|
|
|
|
if (alt_dis_format) { // use ARM register names for disassembly
|
|
reg_name = &alt_arm_reg_name[0];
|
|
}
|
|
|
|
sprintf_buffer = di_buffer; // quick 'n' dirty printf() vs sprintf()
|
|
sprintf_buf_len = 39; // should be passed in
|
|
|
|
instr = *(u_int32_t *)loc;
|
|
return (db_disasm_insn(instr, loc, false));
|
|
}
|