260 lines
5.5 KiB
Plaintext
260 lines
5.5 KiB
Plaintext
/*
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* Copyright (C) 2022 Google LLC
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#define PLACEHOLDER 0xffffffff
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#define PLACEHOLDER2 PLACEHOLDER PLACEHOLDER
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#define PLACEHOLDER4 PLACEHOLDER2 PLACEHOLDER2
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#define IRQ_BASE 4
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/dts-v1/;
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/ {
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interrupt-parent = <&intc>;
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compatible = "linux,dummy-virt";
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#address-cells = <2>;
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#size-cells = <2>;
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chosen {
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stdout-path = "/uart@3f8";
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linux,pci-probe-only = <1>;
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kaslr-seed = <PLACEHOLDER2>;
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avf,strict-boot;
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avf,new-instance;
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};
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memory {
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device_type = "memory";
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reg = <0x00 0x80000000 PLACEHOLDER2>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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swiotlb: restricted_dma_reserved {
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compatible = "restricted-dma-pool";
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size = <PLACEHOLDER2>;
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alignment = <PLACEHOLDER2>;
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};
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dice {
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compatible = "google,open-dice";
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no-map;
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reg = <PLACEHOLDER4>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,arm-v8";
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enable-method = "psci";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,arm-v8";
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enable-method = "psci";
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reg = <1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,arm-v8";
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enable-method = "psci";
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reg = <2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,arm-v8";
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enable-method = "psci";
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reg = <3>;
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};
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cpu@4 {
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device_type = "cpu";
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compatible = "arm,arm-v8";
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enable-method = "psci";
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reg = <4>;
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};
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cpu@5 {
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device_type = "cpu";
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compatible = "arm,arm-v8";
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enable-method = "psci";
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reg = <5>;
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};
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cpu@6 {
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device_type = "cpu";
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compatible = "arm,arm-v8";
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enable-method = "psci";
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reg = <6>;
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};
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cpu@7 {
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device_type = "cpu";
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compatible = "arm,arm-v8";
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enable-method = "psci";
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reg = <7>;
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};
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cpu@8 {
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device_type = "cpu";
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compatible = "arm,arm-v8";
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enable-method = "psci";
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reg = <8>;
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};
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cpu@9 {
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device_type = "cpu";
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compatible = "arm,arm-v8";
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enable-method = "psci";
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reg = <9>;
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};
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cpu@10 {
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device_type = "cpu";
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compatible = "arm,arm-v8";
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enable-method = "psci";
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reg = <10>;
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};
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cpu@11 {
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device_type = "cpu";
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compatible = "arm,arm-v8";
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enable-method = "psci";
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reg = <11>;
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};
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cpu@12 {
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device_type = "cpu";
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compatible = "arm,arm-v8";
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enable-method = "psci";
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reg = <12>;
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};
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cpu@13 {
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device_type = "cpu";
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compatible = "arm,arm-v8";
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enable-method = "psci";
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reg = <13>;
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};
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cpu@14 {
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device_type = "cpu";
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compatible = "arm,arm-v8";
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enable-method = "psci";
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reg = <14>;
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};
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cpu@15 {
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device_type = "cpu";
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compatible = "arm,arm-v8";
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enable-method = "psci";
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reg = <15>;
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};
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};
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intc: intc {
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compatible = "arm,gic-v3";
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#address-cells = <2>;
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#size-cells = <2>;
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x00 0x3fff0000 0x00 0x10000>, <PLACEHOLDER4>;
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};
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timer {
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compatible = "arm,armv8-timer";
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always-on;
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/* The IRQ type needs to be OR-ed with the CPU mask */
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interrupts = <GIC_PPI 0xd IRQ_TYPE_LEVEL_LOW
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GIC_PPI 0xe IRQ_TYPE_LEVEL_LOW
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GIC_PPI 0xb IRQ_TYPE_LEVEL_LOW
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GIC_PPI 0xa IRQ_TYPE_LEVEL_LOW>;
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};
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uart@2e8 {
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compatible = "ns16550a";
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reg = <0x00 0x2e8 0x00 0x8>;
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clock-frequency = <0x1c2000>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>;
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};
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uart@2f8 {
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compatible = "ns16550a";
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reg = <0x00 0x2f8 0x00 0x8>;
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clock-frequency = <0x1c2000>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>;
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};
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uart@3e8 {
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compatible = "ns16550a";
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reg = <0x00 0x3e8 0x00 0x8>;
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clock-frequency = <0x1c2000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
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};
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uart@3f8 {
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compatible = "ns16550a";
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reg = <0x00 0x3f8 0x00 0x8>;
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clock-frequency = <0x1c2000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "hvc";
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};
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pci {
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compatible = "pci-host-cam-generic";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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dma-coherent;
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memory-region = <&swiotlb>;
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ranges = <
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0x3000000 0x0 0x02000000 0x0 0x02000000 0x00 0x02000000
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0x3000000 PLACEHOLDER2 PLACEHOLDER2 PLACEHOLDER2
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>;
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bus-range = <0x00 0x00>;
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reg = <0x00 0x10000 0x00 0x1000000>;
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interrupt-map = <
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0x0800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 0) IRQ_TYPE_LEVEL_HIGH
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0x1000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 1) IRQ_TYPE_LEVEL_HIGH
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0x1800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 2) IRQ_TYPE_LEVEL_HIGH
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0x2000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 3) IRQ_TYPE_LEVEL_HIGH
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0x2800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 4) IRQ_TYPE_LEVEL_HIGH
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0x3000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 5) IRQ_TYPE_LEVEL_HIGH
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0x3800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 6) IRQ_TYPE_LEVEL_HIGH
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0x4000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 7) IRQ_TYPE_LEVEL_HIGH
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>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7
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0xf800 0x0 0x0 0x7
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0xf800 0x0 0x0 0x7
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0xf800 0x0 0x0 0x7
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0xf800 0x0 0x0 0x7
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0xf800 0x0 0x0 0x7
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0xf800 0x0 0x0 0x7
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0xf800 0x0 0x0 0x7>;
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};
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clk: pclk@3M {
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compatible = "fixed-clock";
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clock-frequency = <0x2fefd8>;
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#clock-cells = <0>;
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};
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rtc@2000 {
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compatible = "arm,primecell";
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arm,primecell-periphid = <0x41030>;
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reg = <0x00 0x2000 0x00 0x1000>;
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "apb_pclk";
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clocks = <&clk>;
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};
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vmwdt@3000 {
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compatible = "qemu,vcpu-stall-detector";
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reg = <0x00 0x3000 0x00 0x1000>;
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clock-frequency = <10>;
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timeout-sec = <8>;
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};
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};
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