166 lines
4.8 KiB
ArmAsm
166 lines
4.8 KiB
ArmAsm
/*
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* Copyright (C) 2013 The Android Open Source Project
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 2013 ARM Ltd
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the company may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <private/bionic_asm.h>
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.syntax unified
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.thumb
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.thumb_func
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ENTRY(strlen)
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pld [r0, #0]
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mov r1, r0
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ands r3, r0, #7
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beq .L_mainloop
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// Align to a double word (64 bits).
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rsb r3, r3, #8
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lsls ip, r3, #31
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beq .L_align_to_32
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ldrb r2, [r1], #1
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cbz r2, .L_update_count_and_return
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.L_align_to_32:
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bcc .L_align_to_64
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ands ip, r3, #2
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beq .L_align_to_64
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ldrb r2, [r1], #1
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cbz r2, .L_update_count_and_return
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ldrb r2, [r1], #1
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cbz r2, .L_update_count_and_return
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.L_align_to_64:
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tst r3, #4
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beq .L_mainloop
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ldr r3, [r1], #4
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sub ip, r3, #0x01010101
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bic ip, ip, r3
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ands ip, ip, #0x80808080
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bne .L_zero_in_second_register
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.p2align 2
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.L_mainloop:
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ldrd r2, r3, [r1], #8
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pld [r1, #64]
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sub ip, r2, #0x01010101
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bic ip, ip, r2
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ands ip, ip, #0x80808080
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bne .L_zero_in_first_register
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sub ip, r3, #0x01010101
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bic ip, ip, r3
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ands ip, ip, #0x80808080
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bne .L_zero_in_second_register
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b .L_mainloop
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.L_update_count_and_return:
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sub r0, r1, r0
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sub r0, r0, #1
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bx lr
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.L_zero_in_first_register:
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sub r0, r1, r0
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lsls r3, ip, #17
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bne .L_sub8_and_return
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bcs .L_sub7_and_return
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lsls ip, ip, #1
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bne .L_sub6_and_return
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sub r0, r0, #5
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bx lr
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.L_sub8_and_return:
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sub r0, r0, #8
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bx lr
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.L_sub7_and_return:
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sub r0, r0, #7
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bx lr
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.L_sub6_and_return:
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sub r0, r0, #6
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bx lr
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.L_zero_in_second_register:
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sub r0, r1, r0
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lsls r3, ip, #17
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bne .L_sub4_and_return
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bcs .L_sub3_and_return
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lsls ip, ip, #1
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bne .L_sub2_and_return
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sub r0, r0, #1
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bx lr
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.L_sub4_and_return:
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sub r0, r0, #4
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bx lr
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.L_sub3_and_return:
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sub r0, r0, #3
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bx lr
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.L_sub2_and_return:
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sub r0, r0, #2
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bx lr
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END(strlen)
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