235 lines
6.4 KiB
ArmAsm
235 lines
6.4 KiB
ArmAsm
/*
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* Copyright (c) 1997 Mark Brinicombe
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* Copyright (c) 2010 Android Open Source Project.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Mark Brinicombe
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <private/bionic_asm.h>
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// According to the ARM AAPCS document, we only need to save
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// the following registers:
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//
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// Core r4-r14
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//
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// VFP d8-d15 (see section 5.1.2.1)
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//
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// Registers s16-s31 (d8-d15, q4-q7) must be preserved across subroutine
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// calls; registers s0-s15 (d0-d7, q0-q3) do not need to be preserved
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// (and can be used for passing arguments or returning results in standard
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// procedure-call variants). Registers d16-d31 (q8-q15), if present, do
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// not need to be preserved.
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//
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// FPSCR saved because glibc does.
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// The internal structure of a jmp_buf is totally private.
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// Current layout (may change in the future):
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//
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// word name description
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// 0 sigflag/cookie setjmp cookie in top 31 bits, signal mask flag in low bit
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// 1 sigmask signal mask (not used with _setjmp / _longjmp)
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// 2 float_base base of float registers (d8 to d15)
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// 18 float_state floating-point status and control register
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// 19 core_base base of core registers (r4 to r14)
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// 30 reserved reserved entries (room to grow)
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// 64
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//
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// NOTE: float_base must be at an even word index, since the
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// FP registers will be loaded/stored with instructions
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// that expect 8-byte alignment.
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#define _JB_SIGFLAG 0
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#define _JB_SIGMASK (_JB_SIGFLAG+1)
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#define _JB_FLOAT_BASE (_JB_SIGMASK+1)
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#define _JB_FLOAT_STATE (_JB_FLOAT_BASE + (15-8+1)*2)
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#define _JB_CORE_BASE (_JB_FLOAT_STATE+1)
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ENTRY(setjmp)
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mov r1, #1
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b sigsetjmp
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END(setjmp)
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ENTRY(_setjmp)
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mov r1, #0
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b sigsetjmp
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END(_setjmp)
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#define MANGLE_REGISTERS 1
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.macro m_mangle_registers reg
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#if MANGLE_REGISTERS
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eor r4, r4, \reg
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eor r5, r5, \reg
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eor r6, r6, \reg
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eor r7, r7, \reg
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eor r8, r8, \reg
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eor r9, r9, \reg
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eor r10, r10, \reg
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eor r11, r11, \reg
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eor r12, r12, \reg
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eor r13, r13, \reg
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eor r14, r14, \reg
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#endif
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.endm
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.macro m_unmangle_registers reg
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m_mangle_registers \reg
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.endm
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// int sigsetjmp(sigjmp_buf env, int save_signal_mask);
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ENTRY(sigsetjmp)
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stmfd sp!, {r0, lr}
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.cfi_def_cfa_offset 8
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.cfi_rel_offset r0, 0
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.cfi_rel_offset lr, 4
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mov r0, r1
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bl __bionic_setjmp_cookie_get
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mov r1, r0
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ldmfd sp, {r0}
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// Save the setjmp cookie for later.
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bic r2, r1, #1
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stmfd sp!, {r2}
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.cfi_adjust_cfa_offset 4
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// Record the setjmp cookie and whether or not we're saving the signal mask.
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str r1, [r0, #(_JB_SIGFLAG * 4)]
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// Do we need to save the signal mask?
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tst r1, #1
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beq 1f
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// Align the stack.
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sub sp, #4
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.cfi_adjust_cfa_offset 4
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// Save the current signal mask.
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add r2, r0, #(_JB_SIGMASK * 4)
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mov r0, #2 // SIG_SETMASK
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mov r1, #0
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bl sigprocmask
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// Unalign the stack.
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add sp, #4
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.cfi_adjust_cfa_offset -4
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1:
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ldmfd sp!, {r2}
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.cfi_adjust_cfa_offset -4
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ldmfd sp!, {r0, lr}
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.cfi_adjust_cfa_offset -8
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.cfi_restore r0
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.cfi_restore lr
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// Save core registers.
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add r1, r0, #(_JB_CORE_BASE * 4)
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m_mangle_registers r2
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// ARM deprecates using sp in the register list for stmia.
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stmia r1, {r4-r12, lr}
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str sp, [r1, #(10 * 4)]
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m_unmangle_registers r2
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// Save floating-point registers.
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add r1, r0, #(_JB_FLOAT_BASE * 4)
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vstmia r1, {d8-d15}
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// Save floating-point state.
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fmrx r1, fpscr
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str r1, [r0, #(_JB_FLOAT_STATE * 4)]
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mov r0, #0
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bx lr
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END(sigsetjmp)
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// void siglongjmp(sigjmp_buf env, int value);
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ENTRY(siglongjmp)
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stmfd sp!, {r0, r1, lr}
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.cfi_def_cfa_offset 12
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.cfi_rel_offset r0, 0
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.cfi_rel_offset r1, 4
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.cfi_rel_offset lr, 8
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// Fetch the signal flag.
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ldr r1, [r0, #(_JB_SIGFLAG * 4)]
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// Do we need to restore the signal mask?
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ands r1, r1, #1
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beq 1f
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// Restore the signal mask.
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ldr r0, [r0, #(_JB_SIGMASK * 4)]
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bl sigsetmask
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1:
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ldmfd sp!, {r0, r1, lr}
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.cfi_adjust_cfa_offset -12
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.cfi_restore r0
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.cfi_restore r1
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.cfi_restore lr
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// Restore floating-point registers.
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add r2, r0, #(_JB_FLOAT_BASE * 4)
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vldmia r2, {d8-d15}
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// Restore floating-point state.
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ldr r2, [r0, #(_JB_FLOAT_STATE * 4)]
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fmxr fpscr, r2
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// Restore core registers.
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ldr r3, [r0, #(_JB_SIGFLAG * 4)]
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bic r3, r3, #1
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add r2, r0, #(_JB_CORE_BASE * 4)
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// ARM deprecates using sp in the register list for ldmia.
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ldmia r2, {r4-r12, lr}
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ldr sp, [r2, #(10 * 4)]
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m_unmangle_registers r3
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// Save the return value/address and check the setjmp cookie.
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stmfd sp!, {r1, lr}
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.cfi_adjust_cfa_offset 8
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.cfi_rel_offset lr, 4
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mov r0, r3
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bl __bionic_setjmp_cookie_check
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// Restore return value/address.
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ldmfd sp!, {r0, lr}
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.cfi_adjust_cfa_offset -8
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.cfi_restore lr
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teq r0, #0
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moveq r0, #1
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bx lr
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END(siglongjmp)
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ALIAS_SYMBOL(longjmp, siglongjmp)
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ALIAS_SYMBOL(_longjmp, siglongjmp)
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