Commit Graph

37348 Commits

Author SHA1 Message Date
Elliott Hughes 473dcc59f3 Remove Commodore 64 support.
https://en.wikipedia.org/wiki/KERNAL

Test: treehugger
Change-Id: I42fc21daa051eca29e6bda7f29c81dd8f353c14e
2022-10-19 16:13:09 +00:00
Yu Liu 0b67417d77 Merge "Refactor the bp file to avoid arch variant in cc_genrule." 2022-10-19 15:27:08 +00:00
Treehugger Robot d33a5c63a8 Merge "riscv64: fix <fenv.h> tests." 2022-10-19 04:20:36 +00:00
Treehugger Robot 017aec5f61 Merge "riscv64: fix setjmp so we're actually using the right cookie!" 2022-10-19 00:51:49 +00:00
Yu Liu 938ec9b7e8 Refactor the bp file to avoid arch variant in cc_genrule.
The arch variant of genrule.out will be soon disallowed in soong.

Bug: 253645813
Test: Manually build.
Change-Id: I2d5daa67b4e10f4abddebc98775df18df485843f
2022-10-18 17:23:17 -07:00
Treehugger Robot 5a4a2fec44 Merge "arm64: simplify the fenv implementation a bit." 2022-10-19 00:09:10 +00:00
Elliott Hughes 017bd9882a riscv64: fix <fenv.h> tests.
Group riscv64 with arm/arm64, and allow for the fact that there's no
FE_DENORMAL in the riscv64 spec.

Test: fenv.*
Change-Id: Ibf188bcedffd092a7ef1555fa2762e249e1f9845
2022-10-18 23:47:28 +00:00
Elliott Hughes 45a84869c4 riscv64: fix setjmp so we're actually using the right cookie!
Test: setjmp.setjmp_smoke
Change-Id: Ia0a160656b9e83cdec611ac196b1ae62f082ab6c
2022-10-18 23:04:12 +00:00
Treehugger Robot e24dd597e7 Merge "riscv64: don't store both arguments in the same place on the stack." 2022-10-18 22:05:08 +00:00
Elliott Hughes c800a3bd02 riscv64: don't store both arguments in the same place on the stack.
All the pthread tests are, unsurprisingly, broken without this fix.

Test: treehugger
Change-Id: Ia4c6ac077f3bbd749201ae8d200ec99093f7f4bc
2022-10-18 20:01:58 +00:00
Treehugger Robot 8333532f3b Merge "Revert "Refactor the bp file to avoid arch variant in cc_genrule."" 2022-10-18 04:48:28 +00:00
Treehugger Robot b15a64f722 Merge "riscv64 setjmp." 2022-10-18 04:09:55 +00:00
Yu Liu 3a57969a6f Revert "Refactor the bp file to avoid arch variant in cc_genrule."
This reverts commit ed2654cfdc.

Reason for revert: breaks aosp-master

Change-Id: I8236e3e31e208e8719df52f6b1488af919b37d94
2022-10-18 03:02:32 +00:00
Yu Liu 86ef94783b Merge "Refactor the bp file to avoid arch variant in cc_genrule." 2022-10-18 02:19:03 +00:00
Yu Liu ed2654cfdc Refactor the bp file to avoid arch variant in cc_genrule.
The arch variant of genrule.out will be soon disallowed in soong.

Bug: 253645813
Test: Manually build.
Change-Id: Ia07d45195de8c22f18487aef34795279d2962c4c
2022-10-17 16:36:30 -07:00
Elliott Hughes e1905ed629 riscv64 setjmp.
Signed-off-by: Mao Han <han_mao@linux.alibaba.com>
Signed-off-by: Xia Lifang <lifang_xia@linux.alibaba.com>
Signed-off-by: Chen Guoyin <chenguoyin.cgy@linux.alibaba.com>
Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
Signed-off-by: Lu Xufan <luxufan@iscas.ac.cn>
Test: m
Change-Id: I02cf117f67bda74516e4de8cd6f4c05efdb9a85b
2022-10-17 23:23:36 +00:00
Treehugger Robot 5acd891bdb Merge changes I712a9a93,Idd7b3610
* changes:
  Add riscv64 crtbegin assembler.
  riscv64: enable the version scripts.
2022-10-17 23:03:49 +00:00
Elliott Hughes 7a19624698 Add riscv64 crtbegin assembler.
Signed-off-by: Mao Han <han_mao@linux.alibaba.com>
Signed-off-by: Xia Lifang <lifang_xia@linux.alibaba.com>
Signed-off-by: Chen Guoyin <chenguoyin.cgy@linux.alibaba.com>
Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
Signed-off-by: Lu Xufan <luxufan@iscas.ac.cn>
Test: treehugger
Change-Id: I712a9a93a2df208d763bc46175e00ff763b68146
2022-10-17 21:06:19 +00:00
Elliott Hughes 604ab0fe82 riscv64: enable the version scripts.
Test: treehugger
Change-Id: Idd7b3610bd3321d7e1a4e868cf5dbaf2980909ab
2022-10-17 21:06:10 +00:00
Treehugger Robot 81f0bdb6f3 Merge "riscv64: fenv implementation." 2022-10-15 16:31:16 +00:00
Elliott Hughes 6cef594171 Merge "riscv64: add bionic assembler and string functions." 2022-10-15 15:40:49 +00:00
Elliott Hughes a0733976c5 Merge "Add an explicit test that fegetenv()/fesetenv() includes the rounding mode." 2022-10-15 15:37:56 +00:00
Elliott Hughes ebc19a9ccb riscv64: add bionic assembler and string functions.
Pull the portable C string functions from FreeBSD, and do fairly literal
translations of our existing .S files for the bionic-specific stuff.

Test: treehugger
Change-Id: Id42e5b8a51ed73155be020d74edd7011a2103574
2022-10-14 23:25:36 +00:00
Treehugger Robot edc06da0fe Merge "arm64: remove unnecessary duplication of constants in vfork.S." 2022-10-14 23:18:24 +00:00
Elliott Hughes faac8e658c arm64: remove unnecessary duplication of constants in vfork.S.
Test: treehugger
Change-Id: I41fd22bad0581269c88f5b3bb499735ab6ecafd2
2022-10-14 21:36:58 +00:00
Elliott Hughes 6a1b0f3cac riscv64: fenv implementation.
Signed-off-by: Mao Han <han_mao@linux.alibaba.com>
Signed-off-by: Xia Lifang <lifang_xia@linux.alibaba.com>
Signed-off-by: Chen Guoyin <chenguoyin.cgy@linux.alibaba.com>
Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
Signed-off-by: Lu Xufan <luxufan@iscas.ac.cn>
Test: treehugger
Change-Id: I0f0227cd4cb5e78aba1a749f8d8fce296a024dfb
2022-10-14 21:34:18 +00:00
Elliott Hughes d25a5e73f8 Add an explicit test that fegetenv()/fesetenv() includes the rounding mode.
I haven't found this explicitly stated anywhere, but it's how our
existing implementations behave, and it seems obviously implied by
the word "entire" in POSIX's claim that fenv_t "Represents the entire
floating-point environment".

Test: treehugger
Change-Id: Ic8fc993775b4ded57dc88766a7d24d0954f3b56d
2022-10-14 20:55:23 +00:00
Elliott Hughes a93431ca4c arm64: simplify the fenv implementation a bit.
The macOS man page was helpful in advancing my understanding of
feupdateenv() in particular.

Test: treehugger
Change-Id: I511e8b31ac16f3fdf08b42eee5a2e6558ec3b70b
2022-10-14 20:38:35 +00:00
Elliott Hughes 4c2de1fccc Merge "riscv64 syscall stub and seccomp filter generation." 2022-10-14 14:36:29 +00:00
Treehugger Robot 716b48057c Merge "Add REG_S0 to ucontext.h for riscv64" 2022-10-14 00:58:26 +00:00
Elliott Hughes 704772bda0 riscv64 syscall stub and seccomp filter generation.
These are sufficiently intertwined that they need to be done together.
riscv64 is our first primary-only architecture, so that required some
changes. The .bp changes are to support this --- we need to only show
the python scripts the architectures they'll actually be using, rather
than showing them everything and ignoring some of the results.

riscv64 is also the first architecture that post-dates the kernel's
64-bit time work, so there's a bit of extra fiddling needed to handle
the __NR3264_ indirection in the uapi headers.

Signed-off-by: Mao Han <han_mao@linux.alibaba.com>
Signed-off-by: Xia Lifang <lifang_xia@linux.alibaba.com>
Signed-off-by: Chen Guoyin <chenguoyin.cgy@linux.alibaba.com>
Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
Signed-off-by: Lu Xufan <luxufan@iscas.ac.cn>
Test: local builds for x86-64 and riscv64
Change-Id: I74044744e80b312088f805c44fbd667c9bfcdc69
2022-10-13 23:41:53 +00:00
Colin Cross 91529b75cf Add REG_S0 to ucontext.h for riscv64
REG_S0 is needed by Clang's sanitizer runtimes:
https://github.com/llvm/llvm-project/blob/main/compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp#L2218

Test: clang build
Change-Id: Id9a82e977dcbdddf5505495b59057cf4564c9e35
2022-10-13 13:27:18 -07:00
Treehugger Robot 8f548122ad Merge "Build libdl for risc-v." 2022-10-12 03:14:04 +00:00
Elliott Hughes c5e588ad37 Merge "riscv64 TLS support." 2022-10-12 00:35:37 +00:00
Elliott Hughes ed70c17deb Build libdl for risc-v.
An easy one to start with, since there's nothing really in it :-)

Signed-off-by: Mao Han <han_mao@linux.alibaba.com>
Signed-off-by: Xia Lifang <lifang_xia@linux.alibaba.com>
Signed-off-by: Chen Guoyin <chenguoyin.cgy@linux.alibaba.com>
Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
Signed-off-by: Lu Xufan <luxufan@iscas.ac.cn>
Test: built manually
Change-Id: I16028a6f959d0ce43b9c9d5d90db681479505a3e
2022-10-11 19:01:30 +00:00
Treehugger Robot 6987120b30 Merge "riscv64: add "private/bionic_asm.h"." 2022-10-11 02:33:11 +00:00
Treehugger Robot d5b5adfa87 Merge "riscv64: more <sys/ucontext.h>." 2022-10-11 02:15:10 +00:00
Jingwen Chen 7f50756d59 Merge "Use allowlists.go for all bp2build config and remove Android.bp prop." 2022-10-11 00:36:44 +00:00
Elliott Hughes add0c48a4b riscv64: add "private/bionic_asm.h".
Signed-off-by: Mao Han <han_mao@linux.alibaba.com>
Signed-off-by: Xia Lifang <lifang_xia@linux.alibaba.com>
Signed-off-by: Chen Guoyin <chenguoyin.cgy@linux.alibaba.com>
Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
Signed-off-by: Lu Xufan <luxufan@iscas.ac.cn>
Test: treehugger
Change-Id: Iaa7d5584dfd0ec6f0cf6d3d43ae6bdf2261b12f8
2022-10-11 00:04:34 +00:00
Elliott Hughes 287f48e6e5 riscv64: more <sys/ucontext.h>.
Actually, we don't want to reuse the kernel struct ucontext because its
uc_mcontext has the wrong type, which means the fields within that end
up with the wrong names. Add the call site that made that evident, and
update <sys/ucontext.h> appropriately.

Signed-off-by: Mao Han <han_mao@linux.alibaba.com>
Signed-off-by: Xia Lifang <lifang_xia@linux.alibaba.com>
Signed-off-by: Chen Guoyin <chenguoyin.cgy@linux.alibaba.com>
Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
Signed-off-by: Lu Xufan <luxufan@iscas.ac.cn>
Test: treehugger
Change-Id: If1d079afef0d5953aa22d9b0e049cfb0119c7718
2022-10-11 00:01:35 +00:00
Treehugger Robot ea988f43d8 Merge "Add riscv64 <ucontext.h>." 2022-10-10 22:33:10 +00:00
Elliott Hughes 43462707a1 riscv64 TLS support.
Signed-off-by: Mao Han <han_mao@linux.alibaba.com>
Signed-off-by: Xia Lifang <lifang_xia@linux.alibaba.com>
Signed-off-by: Chen Guoyin <chenguoyin.cgy@linux.alibaba.com>
Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
Signed-off-by: Lu Xufan <luxufan@iscas.ac.cn>
Test: treehugger
Change-Id: I14efb4a03a3dc2ec736d7e47a3f8859c886eb9d6
2022-10-10 20:30:24 +00:00
Elliott Hughes 4043e5ea96 Add riscv64 <ucontext.h>.
Signed-off-by: Mao Han <han_mao@linux.alibaba.com>
Signed-off-by: Xia Lifang <lifang_xia@linux.alibaba.com>
Signed-off-by: Chen Guoyin <chenguoyin.cgy@linux.alibaba.com>
Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
Signed-off-by: Lu Xufan <luxufan@iscas.ac.cn>
Test: treehugger
Change-Id: Ieb7cb71cd735b6629d507efb0a5e35ee653e4d20
2022-10-10 20:15:51 +00:00
Elliott Hughes 5b2552a030 Merge "riscv64 <sys/user.h>." 2022-10-10 16:36:10 +00:00
Jingwen Chen 95ca177c58 Use allowlists.go for all bp2build config and remove Android.bp prop.
This was introduced when we didn't have allowlists.

Bug: 251197532
Test: presubmits
Change-Id: I83713dd9a0a059acda8e4565677d0c8c6b966749
2022-10-10 14:35:15 +00:00
Elliott Hughes c6bddf4516 Merge "riscv64 <fenv.h>." 2022-10-08 03:03:13 +00:00
Elliott Hughes e0b9474854 Merge "riscv64 __get_tls()." 2022-10-08 03:02:56 +00:00
Treehugger Robot 002b57c00e Merge "riscv64 BIONIC_STOP_UNWIND." 2022-10-07 23:15:25 +00:00
Treehugger Robot 775112ab88 Merge "Pull in the riscv64 uapi headers for riscv64 builds." 2022-10-07 22:26:49 +00:00
Elliott Hughes fc009dd8a7 riscv64 __get_tls().
Signed-off-by: Mao Han <han_mao@linux.alibaba.com>
Signed-off-by: Xia Lifang <lifang_xia@linux.alibaba.com>
Signed-off-by: Chen Guoyin <chenguoyin.cgy@linux.alibaba.com>
Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
Signed-off-by: Lu Xufan <luxufan@iscas.ac.cn>
Test: treehugger
Change-Id: Ie7616cef6d394ba457c30c58d15f696c9b6d3853
2022-10-07 21:33:57 +00:00