From 3abde068bdefb7d2d7167f66f7037e4eb1b9ce20 Mon Sep 17 00:00:00 2001 From: Elliott Hughes Date: Thu, 18 Feb 2021 15:12:41 -0800 Subject: [PATCH] Inline the raise(SIGABRT) for x86-64 too. This matches what we do for arm and arm64. 32-bit x86 is too big a mess to warrant the effort still, but the more testing is done on cuttlefish, the more value there is to making every stack frame count. Before: #00 pc 00000000000596d8 .../libc.so (syscall+24) #01 pc 000000000005d072 .../libc.so (abort+194) #02 pc 000000000005f1f0 .../libc.so (__fortify_fatal(char const*, ...)+160) After: #00 pc 000000000005d07d .../libc.so (abort+205) #01 pc 000000000005f1e0 .../libc.so (__fortify_fatal(char const*, ...)+160) Test: crasher64 fortify Change-Id: Ib74cb8b36341093c268872e26020f35eb2d8ef66 --- libc/private/bionic_inline_raise.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/libc/private/bionic_inline_raise.h b/libc/private/bionic_inline_raise.h index 7223b4e46..8565c8061 100644 --- a/libc/private/bionic_inline_raise.h +++ b/libc/private/bionic_inline_raise.h @@ -60,8 +60,18 @@ static inline __always_inline void inline_raise(int sig, void* value = nullptr) register long x3 __asm__("x3") = reinterpret_cast(&info); register long x8 __asm__("x8") = __NR_rt_tgsigqueueinfo; __asm__("svc #0" : "=r"(x0) : "r"(x0), "r"(x1), "r"(x2), "r"(x3), "r"(x8) : "memory"); +#elif defined(__x86_64__) + register long rax __asm__("rax") = __NR_rt_tgsigqueueinfo; + register long rdi __asm__("rdi") = pid; + register long rsi __asm__("rsi") = tid; + register long rdx __asm__("rdx") = sig; + register long r10 __asm__("r10") = reinterpret_cast(&info); + __asm__("syscall" + : "+r"(rax) + : "r"(rdi), "r"(rsi), "r"(rdx), "r"(r10) + : "memory", "cc", "r11", "rcx"); #else + // 32-bit x86 is a huge mess, so don't even bother... syscall(__NR_rt_tgsigqueueinfo, pid, tid, sig, &info); #endif } -