Update sys_ptrace_test.cpp for riscv64.

We'll want to come back to this once either Zcmp's push/pop instructions
or V's vector loads/stores are available. But for now, we have no >64b
stores.

But at least this builds.

Test: treehugger
Change-Id: I9503e890cacb198f4ba987bfc92f6eff21c290b0

tests/sys_ptrace_test.cpp

@@ -257,6 +257,9 @@ static void watchpoint_imprecise_child(Uint128_t& data) {
   asm volatile("stm %0, { r0, r1, r2, r3 }" : : "r"(&data));
 #elif defined(__aarch64__)
   asm volatile("stp x0, x1, %0" : : "m"(data));
+#elif defined(__riscv)
+  UNUSED(data);
+  GTEST_LOG_(INFO) << "missing riscv64 instruction to store > 64 bits in one instruction";
 #endif
 }