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android_bionic
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Remove denver from bionic 

Test: bionic unit tests
Bug: 73545680
Change-Id: Ib142bf289ac73a3512ad1f29789ef82027160d78
This commit is contained in:
Haibo Huang 2018-12-03 15:05:16 -08:00
parent c69218d47e
commit 01bfd8934e
15 changed files with 290 additions and 716 deletions
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13
libc/Android.bp
View File

@ -714,8 +714,8 @@ cc_library_static {
"arch-arm/cortex-a53/bionic/__strcat_chk.S",
"arch-arm/cortex-a53/bionic/__strcpy_chk.S",
"arch-arm/denver/bionic/__strcat_chk.S",
"arch-arm/denver/bionic/__strcpy_chk.S",
"arch-arm/cortex-a55/bionic/__strcat_chk.S",
"arch-arm/cortex-a55/bionic/__strcpy_chk.S",
],
},
arm64: {
@ -786,11 +786,9 @@ cc_library_static {
"arch-arm/cortex-a15/bionic/strlen.S",
"arch-arm/cortex-a7/bionic/memcpy.S",
"arch-arm/cortex-a7/bionic/memmove.S",
"arch-arm/cortex-a7/bionic/memset.S",
"arch-arm/cortex-a9/bionic/memcpy.S",
"arch-arm/cortex-a9/bionic/memmove.S",
"arch-arm/cortex-a9/bionic/memset.S",
"arch-arm/cortex-a9/bionic/stpcpy.S",
"arch-arm/cortex-a9/bionic/strcat.S",
@ -799,19 +797,14 @@ cc_library_static {
"arch-arm/cortex-a9/bionic/strlen.S",
"arch-arm/krait/bionic/memcpy.S",
"arch-arm/krait/bionic/memmove.S",
"arch-arm/krait/bionic/memset.S",
"arch-arm/krait/bionic/strcmp.S",
"arch-arm/cortex-a53/bionic/memcpy.S",
"arch-arm/cortex-a53/bionic/memmove.S",
"arch-arm/denver/bionic/memcpy.S",
"arch-arm/denver/bionic/memmove.S",
"arch-arm/denver/bionic/memset.S",
"arch-arm/cortex-a55/bionic/memcpy.S",
"arch-arm/kryo/bionic/memcpy.S",
"arch-arm/kryo/bionic/memmove.S",
],
},
arm64: {

29
libc/NOTICE
View File

@ -808,35 +808,6 @@ SUCH DAMAGE.
-------------------------------------------------------------------
Copyright (C) 2013 The Android Open Source Project
Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
SUCH DAMAGE.
-------------------------------------------------------------------
Copyright (C) 2014 The Android Open Source Project
Licensed under the Apache License, Version 2.0 (the "License");

256
libc/arch-arm/cortex-a15/bionic/memmove.S
View File

@ -1,6 +1,7 @@
/*
* Copyright (C) 2018 The Android Open Source Project
* Copyright (C) 2013 The Android Open Source Project
* All rights reserved.
* Copyright (c) 2013-2014 NVIDIA Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -26,7 +27,254 @@
* SUCH DAMAGE.
*/
#define MEMMOVE memmove_a15
#define MEMCPY __memcpy_a15
#include <private/bionic_asm.h>
#include <arch-arm/denver/bionic/memmove.S>
.text
.syntax unified
.fpu neon
#define CACHE_LINE_SIZE (64)
#define MEMCPY_BLOCK_SIZE_SMALL (32768)
#define MEMCPY_BLOCK_SIZE_MID (1048576)
#define PREFETCH_DISTANCE_NEAR (CACHE_LINE_SIZE*4)
#define PREFETCH_DISTANCE_MID (CACHE_LINE_SIZE*4)
#define PREFETCH_DISTANCE_FAR (CACHE_LINE_SIZE*16)
ENTRY(memmove_a15)
cmp r2, #0
cmpne r0, r1
bxeq lr
subs r3, r0, r1
bls .L_jump_to_memcpy
cmp r2, r3
bhi .L_reversed_memcpy
.L_jump_to_memcpy:
b __memcpy
.L_reversed_memcpy:
push {r0, lr}
.cfi_def_cfa_offset 8
.cfi_rel_offset r0, 0
.cfi_rel_offset lr, 4
add r0, r0, r2
add r1, r1, r2
/* preload next cache line */
pld [r1, #-CACHE_LINE_SIZE]
pld [r1, #-CACHE_LINE_SIZE*2]
.L_reversed_memcpy_align_dest:
/* Deal with very small blocks (< 32bytes) asap */
cmp r2, #32
blo .L_reversed_memcpy_lt_32bytes
/* no need to align if len < 128 bytes */
cmp r2, #128
blo .L_reversed_memcpy_lt_128bytes
/* align destination to 64 bytes (1 cache line) */
ands r3, r0, #0x3f
beq .L_reversed_memcpy_dispatch
sub r2, r2, r3
0: /* copy 1 byte */
movs ip, r3, lsl #31
ldrbmi ip, [r1, #-1]!
strbmi ip, [r0, #-1]!
1: /* copy 2 bytes */
ldrbcs ip, [r1, #-1]!
strbcs ip, [r0, #-1]!
ldrbcs ip, [r1, #-1]!
strbcs ip, [r0, #-1]!
2: /* copy 4 bytes */
movs ip, r3, lsl #29
bpl 3f
sub r1, r1, #4
sub r0, r0, #4
vld4.8 {d0[0], d1[0], d2[0], d3[0]}, [r1]
vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [r0, :32]
3: /* copy 8 bytes */
bcc 4f
sub r1, r1, #8
sub r0, r0, #8
vld1.8 {d0}, [r1]
vst1.8 {d0}, [r0, :64]
4: /* copy 16 bytes */
movs ip, r3, lsl #27
bpl 5f
sub r1, r1, #16
sub r0, r0, #16
vld1.8 {q0}, [r1]
vst1.8 {q0}, [r0, :128]
5: /* copy 32 bytes */
bcc .L_reversed_memcpy_dispatch
sub r1, r1, #32
sub r0, r0, #32
vld1.8 {q0, q1}, [r1]
vst1.8 {q0, q1}, [r0, :256]
.L_reversed_memcpy_dispatch:
/* preload more cache lines */
pld [r1, #-CACHE_LINE_SIZE*3]
pld [r1, #-CACHE_LINE_SIZE*4]
cmp r2, #MEMCPY_BLOCK_SIZE_SMALL
blo .L_reversed_memcpy_neon_pld_near
cmp r2, #MEMCPY_BLOCK_SIZE_MID
blo .L_reversed_memcpy_neon_pld_mid
b .L_reversed_memcpy_neon_pld_far
.L_reversed_memcpy_neon_pld_near:
/* less than 128 bytes? */
subs r2, r2, #128
blo 1f
sub r1, r1, #32
sub r0, r0, #32
mov r3, #-32
.align 4
0:
/* copy 128 bytes in each loop */
subs r2, r2, #128
/* preload to cache */
pld [r1, #-(PREFETCH_DISTANCE_NEAR+CACHE_LINE_SIZE*2)+32]
/* copy a cache line */
vld1.8 {q0, q1}, [r1], r3
vst1.8 {q0, q1}, [r0, :256], r3
vld1.8 {q0, q1}, [r1], r3
vst1.8 {q0, q1}, [r0, :256], r3
/* preload to cache */
pld [r1, #-(PREFETCH_DISTANCE_NEAR+CACHE_LINE_SIZE*2)+32]
/* copy a cache line */
vld1.8 {q0, q1}, [r1], r3
vst1.8 {q0, q1}, [r0, :256], r3
vld1.8 {q0, q1}, [r1], r3
vst1.8 {q0, q1}, [r0, :256], r3
bhs 0b
add r1, r1, #32
add r0, r0, #32
1:
adds r2, r2, #128
bne .L_reversed_memcpy_lt_128bytes
pop {r0, pc}
.L_reversed_memcpy_neon_pld_mid:
subs r2, r2, #128
sub r1, r1, #32
sub r0, r0, #32
mov r3, #-32
.align 4
0:
/* copy 128 bytes in each loop */
subs r2, r2, #128
/* preload to cache */
pld [r1, #-(PREFETCH_DISTANCE_MID+CACHE_LINE_SIZE)+32]
/* copy a cache line */
vld1.8 {q0, q1}, [r1], r3
vst1.8 {q0, q1}, [r0, :256], r3
vld1.8 {q0, q1}, [r1], r3
vst1.8 {q0, q1}, [r0, :256], r3
/* preload to cache */
pld [r1, #-(PREFETCH_DISTANCE_MID+CACHE_LINE_SIZE)+32]
/* copy a cache line */
vld1.8 {q0, q1}, [r1], r3
vst1.8 {q0, q1}, [r0, :256], r3
vld1.8 {q0, q1}, [r1], r3
vst1.8 {q0, q1}, [r0, :256], r3
bhs 0b
add r1, r1, #32
add r0, r0, #32
1:
adds r2, r2, #128
bne .L_reversed_memcpy_lt_128bytes
pop {r0, pc}
.L_reversed_memcpy_neon_pld_far:
sub r2, r2, #128
sub r0, r0, #128
sub r1, r1, #128
.align 4
0:
/* copy 128 bytes in each loop */
subs r2, r2, #128
/* preload to cache */
pld [r1, #-(PREFETCH_DISTANCE_FAR+CACHE_LINE_SIZE*2)+128]
pld [r1, #-(PREFETCH_DISTANCE_FAR+CACHE_LINE_SIZE)+128]
/* read */
vld1.8 {q0, q1}, [r1]!
vld1.8 {q2, q3}, [r1]!
vld1.8 {q8, q9}, [r1]!
vld1.8 {q10, q11}, [r1]!
/* write */
vst1.8 {q0, q1}, [r0, :256]!
vst1.8 {q2, q3}, [r0, :256]!
vst1.8 {q8, q9}, [r0, :256]!
vst1.8 {q10, q11}, [r0, :256]!
sub r0, r0, #256
sub r1, r1, #256
bhs 0b
add r0, r0, #128
add r1, r1, #128
1:
adds r2, r2, #128
bne .L_reversed_memcpy_lt_128bytes
pop {r0, pc}
.L_reversed_memcpy_lt_128bytes:
6: /* copy 64 bytes */
movs ip, r2, lsl #26
bcc 5f
sub r1, r1, #32
sub r0, r0, #32
vld1.8 {q0, q1}, [r1]
vst1.8 {q0, q1}, [r0]
sub r1, r1, #32
sub r0, r0, #32
vld1.8 {q0, q1}, [r1]
vst1.8 {q0, q1}, [r0]
5: /* copy 32 bytes */
bpl 4f
sub r1, r1, #32
sub r0, r0, #32
vld1.8 {q0, q1}, [r1]
vst1.8 {q0, q1}, [r0]
.L_reversed_memcpy_lt_32bytes:
4: /* copy 16 bytes */
movs ip, r2, lsl #28
bcc 3f
sub r1, r1, #16
sub r0, r0, #16
vld1.8 {q0}, [r1]
vst1.8 {q0}, [r0]
3: /* copy 8 bytes */
bpl 2f
sub r1, r1, #8
sub r0, r0, #8
vld1.8 {d0}, [r1]
vst1.8 {d0}, [r0]
2: /* copy 4 bytes */
ands ip, r2, #0x4
beq 1f
sub r1, r1, #4
sub r0, r0, #4
vld4.8 {d0[0], d1[0], d2[0], d3[0]}, [r1]
vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [r0]
1: /* copy 2 bytes */
movs ip, r2, lsl #31
ldrbcs ip, [r1, #-1]!
strbcs ip, [r0, #-1]!
ldrbcs ip, [r1, #-1]!
strbcs ip, [r0, #-1]!
0: /* copy 1 byte */
ldrbmi ip, [r1, #-1]!
strbmi ip, [r0, #-1]!
pop {r0, pc}
END(memmove_a15)

32
libc/arch-arm/cortex-a53/bionic/memmove.S
View File

@ -1,32 +0,0 @@
/*
* Copyright (C) 2018 The Android Open Source Project
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#define MEMMOVE memmove_a53
#define MEMCPY __memcpy_a53
#include <arch-arm/denver/bionic/memmove.S>

8
libc/arch-arm/denver/bionic/__strcat_chk.S → libc/arch-arm/cortex-a55/bionic/__strcat_chk.S
View File

@ -40,7 +40,7 @@
// Get the length of src string, then get the source of the dst string.
// Check that the two lengths together don't exceed the threshold, then
// do a memcpy of the data.
ENTRY(__strcat_chk_denver)
ENTRY(__strcat_chk_a55)
pld [r0, #0]
push {r0, lr}
.cfi_def_cfa_offset 8
@ -190,9 +190,9 @@ ENTRY(__strcat_chk_denver)
mov r2, r4
add r0, r0, r3
pop {r4, r5}
END(__strcat_chk_denver)
END(__strcat_chk_a55)
#define MEMCPY_BASE __strcat_chk_denver_memcpy_base
#define MEMCPY_BASE_ALIGNED __strcat_chk_denver_memcpy_base_aligned
#define MEMCPY_BASE __strcat_chk_a55_memcpy_base
#define MEMCPY_BASE_ALIGNED __strcat_chk_a55_memcpy_base_aligned
#include "memcpy_base.S"

8
libc/arch-arm/denver/bionic/__strcpy_chk.S → libc/arch-arm/cortex-a55/bionic/__strcpy_chk.S
View File

@ -39,7 +39,7 @@
// Get the length of the source string first, then do a memcpy of the data
// instead of a strcpy.
ENTRY(__strcpy_chk_denver)
ENTRY(__strcpy_chk_a55)
pld [r0, #0]
push {r0, lr}
.cfi_def_cfa_offset 8
@ -161,8 +161,8 @@ ENTRY(__strcpy_chk_denver)
bhi __strcpy_chk_fail
// Fall through into the memcpy_base function.
END(__strcpy_chk_denver)
END(__strcpy_chk_a55)
#define MEMCPY_BASE __strcpy_chk_denver_memcpy_base
#define MEMCPY_BASE_ALIGNED __strcpy_chk_denver_memcpy_base_aligned
#define MEMCPY_BASE __strcpy_chk_a55_memcpy_base
#define MEMCPY_BASE_ALIGNED __strcpy_chk_a55_memcpy_base_aligned
#include "memcpy_base.S"

8
libc/arch-arm/denver/bionic/memcpy.S → libc/arch-arm/cortex-a55/bionic/memcpy.S
View File

@ -65,14 +65,14 @@
// arch. The code generated is exactly the same.
.arch armv7-a
ENTRY(__memcpy_denver)
ENTRY(__memcpy_a55)
pld [r1, #64]
push {r0, lr}
.cfi_def_cfa_offset 8
.cfi_rel_offset r0, 0
.cfi_rel_offset lr, 4
END(__memcpy_denver)
END(__memcpy_a55)
#define MEMCPY_BASE __memcpy_base_denver
#define MEMCPY_BASE_ALIGNED __memcpy_base_aligned_denver
#define MEMCPY_BASE __memcpy_base_a55
#define MEMCPY_BASE_ALIGNED __memcpy_base_aligned_a55
#include "memcpy_base.S"

0
libc/arch-arm/denver/bionic/memcpy_base.S → libc/arch-arm/cortex-a55/bionic/memcpy_base.S
View File

32
libc/arch-arm/cortex-a7/bionic/memmove.S
View File

@ -1,32 +0,0 @@
/*
* Copyright (C) 2018 The Android Open Source Project
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#define MEMMOVE memmove_a7
#define MEMCPY __memcpy_a7
#include <arch-arm/denver/bionic/memmove.S>

32
libc/arch-arm/cortex-a9/bionic/memmove.S
View File

@ -1,32 +0,0 @@
/*
* Copyright (C) 2018 The Android Open Source Project
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#define MEMMOVE memmove_a9
#define MEMCPY __memcpy_a9
#include <arch-arm/denver/bionic/memmove.S>

288
libc/arch-arm/denver/bionic/memmove.S
View File

@ -1,288 +0,0 @@
/*
* Copyright (C) 2013 The Android Open Source Project
* All rights reserved.
* Copyright (c) 2013-2014 NVIDIA Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <private/bionic_asm.h>
#ifndef MEMMOVE
# define MEMMOVE memmove_denver
#endif
#ifndef MEMCPY
# define MEMCPY __memcpy_denver
#endif
.text
.syntax unified
.fpu neon
#define CACHE_LINE_SIZE (64)
#define MEMCPY_BLOCK_SIZE_SMALL (32768)
#define MEMCPY_BLOCK_SIZE_MID (1048576)
#define PREFETCH_DISTANCE_NEAR (CACHE_LINE_SIZE*4)
#define PREFETCH_DISTANCE_MID (CACHE_LINE_SIZE*4)
#define PREFETCH_DISTANCE_FAR (CACHE_LINE_SIZE*16)
ENTRY(MEMMOVE)
cmp r2, #0
cmpne r0, r1
bxeq lr
subs r3, r0, r1
bls .L_jump_to_memcpy
cmp r2, r3
bhi .L_reversed_memcpy
.L_jump_to_memcpy:
b MEMCPY
.L_reversed_memcpy:
push {r0, lr}
.cfi_def_cfa_offset 8
.cfi_rel_offset r0, 0
.cfi_rel_offset lr, 4
add r0, r0, r2
add r1, r1, r2
/* preload next cache line */
pld [r1, #-CACHE_LINE_SIZE]
pld [r1, #-CACHE_LINE_SIZE*2]
.L_reversed_memcpy_align_dest:
/* Deal with very small blocks (< 32bytes) asap */
cmp r2, #32
blo .L_reversed_memcpy_lt_32bytes
/* no need to align if len < 128 bytes */
cmp r2, #128
blo .L_reversed_memcpy_lt_128bytes
/* align destination to 64 bytes (1 cache line) */
ands r3, r0, #0x3f
beq .L_reversed_memcpy_dispatch
sub r2, r2, r3
0: /* copy 1 byte */
movs ip, r3, lsl #31
ldrbmi ip, [r1, #-1]!
strbmi ip, [r0, #-1]!
1: /* copy 2 bytes */
ldrbcs ip, [r1, #-1]!
strbcs ip, [r0, #-1]!
ldrbcs ip, [r1, #-1]!
strbcs ip, [r0, #-1]!
2: /* copy 4 bytes */
movs ip, r3, lsl #29
bpl 3f
sub r1, r1, #4
sub r0, r0, #4
vld4.8 {d0[0], d1[0], d2[0], d3[0]}, [r1]
vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [r0, :32]
3: /* copy 8 bytes */
bcc 4f
sub r1, r1, #8
sub r0, r0, #8
vld1.8 {d0}, [r1]
vst1.8 {d0}, [r0, :64]
4: /* copy 16 bytes */
movs ip, r3, lsl #27
bpl 5f
sub r1, r1, #16
sub r0, r0, #16
vld1.8 {q0}, [r1]
vst1.8 {q0}, [r0, :128]
5: /* copy 32 bytes */
bcc .L_reversed_memcpy_dispatch
sub r1, r1, #32
sub r0, r0, #32
vld1.8 {q0, q1}, [r1]
vst1.8 {q0, q1}, [r0, :256]
.L_reversed_memcpy_dispatch:
/* preload more cache lines */
pld [r1, #-CACHE_LINE_SIZE*3]
pld [r1, #-CACHE_LINE_SIZE*4]
cmp r2, #MEMCPY_BLOCK_SIZE_SMALL
blo .L_reversed_memcpy_neon_pld_near
cmp r2, #MEMCPY_BLOCK_SIZE_MID
blo .L_reversed_memcpy_neon_pld_mid
b .L_reversed_memcpy_neon_pld_far
.L_reversed_memcpy_neon_pld_near:
/* less than 128 bytes? */
subs r2, r2, #128
blo 1f
sub r1, r1, #32
sub r0, r0, #32
mov r3, #-32
.align 4
0:
/* copy 128 bytes in each loop */
subs r2, r2, #128
/* preload to cache */
pld [r1, #-(PREFETCH_DISTANCE_NEAR+CACHE_LINE_SIZE*2)+32]
/* copy a cache line */
vld1.8 {q0, q1}, [r1], r3
vst1.8 {q0, q1}, [r0, :256], r3
vld1.8 {q0, q1}, [r1], r3
vst1.8 {q0, q1}, [r0, :256], r3
/* preload to cache */
pld [r1, #-(PREFETCH_DISTANCE_NEAR+CACHE_LINE_SIZE*2)+32]
/* copy a cache line */
vld1.8 {q0, q1}, [r1], r3
vst1.8 {q0, q1}, [r0, :256], r3
vld1.8 {q0, q1}, [r1], r3
vst1.8 {q0, q1}, [r0, :256], r3
bhs 0b
add r1, r1, #32
add r0, r0, #32
1:
adds r2, r2, #128
bne .L_reversed_memcpy_lt_128bytes
pop {r0, pc}
.L_reversed_memcpy_neon_pld_mid:
subs r2, r2, #128
sub r1, r1, #32
sub r0, r0, #32
mov r3, #-32
.align 4
0:
/* copy 128 bytes in each loop */
subs r2, r2, #128
/* preload to cache */
pld [r1, #-(PREFETCH_DISTANCE_MID+CACHE_LINE_SIZE)+32]
/* copy a cache line */
vld1.8 {q0, q1}, [r1], r3
vst1.8 {q0, q1}, [r0, :256], r3
vld1.8 {q0, q1}, [r1], r3
vst1.8 {q0, q1}, [r0, :256], r3
/* preload to cache */
pld [r1, #-(PREFETCH_DISTANCE_MID+CACHE_LINE_SIZE)+32]
/* copy a cache line */
vld1.8 {q0, q1}, [r1], r3
vst1.8 {q0, q1}, [r0, :256], r3
vld1.8 {q0, q1}, [r1], r3
vst1.8 {q0, q1}, [r0, :256], r3
bhs 0b
add r1, r1, #32
add r0, r0, #32
1:
adds r2, r2, #128
bne .L_reversed_memcpy_lt_128bytes
pop {r0, pc}
.L_reversed_memcpy_neon_pld_far:
sub r2, r2, #128
sub r0, r0, #128
sub r1, r1, #128
.align 4
0:
/* copy 128 bytes in each loop */
subs r2, r2, #128
/* preload to cache */
pld [r1, #-(PREFETCH_DISTANCE_FAR+CACHE_LINE_SIZE*2)+128]
pld [r1, #-(PREFETCH_DISTANCE_FAR+CACHE_LINE_SIZE)+128]
/* read */
vld1.8 {q0, q1}, [r1]!
vld1.8 {q2, q3}, [r1]!
vld1.8 {q8, q9}, [r1]!
vld1.8 {q10, q11}, [r1]!
/* write */
vst1.8 {q0, q1}, [r0, :256]!
vst1.8 {q2, q3}, [r0, :256]!
vst1.8 {q8, q9}, [r0, :256]!
vst1.8 {q10, q11}, [r0, :256]!
sub r0, r0, #256
sub r1, r1, #256
bhs 0b
add r0, r0, #128
add r1, r1, #128
1:
adds r2, r2, #128
bne .L_reversed_memcpy_lt_128bytes
pop {r0, pc}
.L_reversed_memcpy_lt_128bytes:
6: /* copy 64 bytes */
movs ip, r2, lsl #26
bcc 5f
sub r1, r1, #32
sub r0, r0, #32
vld1.8 {q0, q1}, [r1]
vst1.8 {q0, q1}, [r0]
sub r1, r1, #32
sub r0, r0, #32
vld1.8 {q0, q1}, [r1]
vst1.8 {q0, q1}, [r0]
5: /* copy 32 bytes */
bpl 4f
sub r1, r1, #32
sub r0, r0, #32
vld1.8 {q0, q1}, [r1]
vst1.8 {q0, q1}, [r0]
.L_reversed_memcpy_lt_32bytes:
4: /* copy 16 bytes */
movs ip, r2, lsl #28
bcc 3f
sub r1, r1, #16
sub r0, r0, #16
vld1.8 {q0}, [r1]
vst1.8 {q0}, [r0]
3: /* copy 8 bytes */
bpl 2f
sub r1, r1, #8
sub r0, r0, #8
vld1.8 {d0}, [r1]
vst1.8 {d0}, [r0]
2: /* copy 4 bytes */
ands ip, r2, #0x4
beq 1f
sub r1, r1, #4
sub r0, r0, #4
vld4.8 {d0[0], d1[0], d2[0], d3[0]}, [r1]
vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [r0]
1: /* copy 2 bytes */
movs ip, r2, lsl #31
ldrbcs ip, [r1, #-1]!
strbcs ip, [r0, #-1]!
ldrbcs ip, [r1, #-1]!
strbcs ip, [r0, #-1]!
0: /* copy 1 byte */
ldrbmi ip, [r1, #-1]!
strbmi ip, [r0, #-1]!
pop {r0, pc}
END(MEMMOVE)

186
libc/arch-arm/denver/bionic/memset.S
View File

@ -1,186 +0,0 @@
/*
* Copyright (C) 2013 The Android Open Source Project
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <private/bionic_asm.h>
/*
* Optimized memset() for ARM.
*
* memset() returns its first argument.
*/
.cpu cortex-a15
.fpu neon
.syntax unified
ENTRY(__memset_chk_denver)
cmp r2, r3
bls memset
// Preserve lr for backtrace.
push {lr}
.cfi_def_cfa_offset 4
.cfi_rel_offset lr, 0
bl __memset_chk_fail
END(__memset_chk_denver)
ENTRY(memset_denver)
pldw [r0]
mov r3, r0
// Duplicate the low byte of r1
mov r1, r1, lsl #24
orr r1, r1, r1, lsr #8
orr r1, r1, r1, lsr #16
cmp r2, #16
blo .L_less_than_16
// This section handles regions 16 bytes or larger
//
// Use aligned vst1.8 and vstm when possible. Register values will be:
// ip is scratch
// q0, q1, and r1 contain the memset value
// r2 is the number of bytes to set
// r3 is the advancing destination pointer
vdup.32 q0, r1
ands ip, r3, 0xF
beq .L_memset_aligned
// Align dest pointer to 16-byte boundary.
pldw [r0, #64]
rsb ip, ip, #16
// Pre-adjust the byte count to reflect post-aligment value. Expecting
// 8-byte alignment to be rather common so we special case that one.
sub r2, r2, ip
/* set 1 byte */
tst ip, #1
it ne
strbne r1, [r3], #1
/* set 2 bytes */
tst ip, #2
it ne
strhne r1, [r3], #2
/* set 4 bytes */
movs ip, ip, lsl #29
it mi
strmi r1, [r3], #4
/* set 8 bytes */
itt cs
strcs r1, [r3], #4
strcs r1, [r3], #4
.L_memset_aligned:
// Destination is now 16-byte aligned. Determine how to handle
// remaining bytes.
vmov q1, q0
cmp r2, #128
blo .L_less_than_128
// We need to set a larger block of memory. Use four Q regs to
// set a full cache line in one instruction. Pre-decrement
// r2 to simplify end-of-loop detection
vmov q2, q0
vmov q3, q0
pldw [r0, #128]
sub r2, r2, #128
.align 4
.L_memset_loop_128:
pldw [r3, #192]
vstm r3!, {q0, q1, q2, q3}
vstm r3!, {q0, q1, q2, q3}
subs r2, r2, #128
bhs .L_memset_loop_128
// Un-bias r2 so it contains the number of bytes left. Early
// exit if we are done.
adds r2, r2, #128
beq 2f
.align 4
.L_less_than_128:
// set 64 bytes
movs ip, r2, lsl #26
bcc 1f
vst1.8 {q0, q1}, [r3, :128]!
vst1.8 {q0, q1}, [r3, :128]!
beq 2f
1:
// set 32 bytes
bpl 1f
vst1.8 {q0, q1}, [r3, :128]!
1:
// set 16 bytes
movs ip, r2, lsl #28
bcc 1f
vst1.8 {q0}, [r3, :128]!
beq 2f
1:
// set 8 bytes
bpl 1f
vst1.8 {d0}, [r3, :64]!
1:
// set 4 bytes
tst r2, #4
it ne
strne r1, [r3], #4
1:
// set 2 bytes
movs ip, r2, lsl #31
it cs
strhcs r1, [r3], #2
// set 1 byte
it mi
strbmi r1, [r3]
2:
bx lr
.L_less_than_16:
// Store up to 15 bytes without worrying about byte alignment
movs ip, r2, lsl #29
bcc 1f
str r1, [r3], #4
str r1, [r3], #4
beq 2f
1:
it mi
strmi r1, [r3], #4
movs ip, r2, lsl #31
it mi
strbmi r1, [r3], #1
itt cs
strbcs r1, [r3], #1
strbcs r1, [r3]
2:
bx lr
END(memset_denver)

50
libc/arch-arm/dynamic_function_dispatch.cpp
View File

@ -38,7 +38,6 @@ enum CpuVariant {
kCortexA9,
kCortexA53,
kCortexA55,
kDenver,
kKrait,
kKryo,
};
@ -59,7 +58,6 @@ static constexpr CpuVariantNames cpu_variant_names[] = {
{"krait", kKrait},
{"cortex-a9", kCortexA9},
{"cortex-a7", kCortexA7},
{"denver", kDenver},
// kUnknown indicates the end of this array.
{"", kUnknown},
};
@ -157,23 +155,7 @@ static CpuVariant get_cpu_variant() {
typedef void* memmove_func(void* __dst, const void* __src, size_t __n);
DEFINE_IFUNC(memmove) {
switch(get_cpu_variant()) {
case kCortexA7:
RETURN_FUNC(memmove_func, memmove_a7);
case kCortexA9:
RETURN_FUNC(memmove_func, memmove_a9);
case kKrait:
RETURN_FUNC(memmove_func, memmove_krait);
case kCortexA53:
RETURN_FUNC(memmove_func, memmove_a53);
case kCortexA55:
case kDenver:
RETURN_FUNC(memmove_func, memmove_denver);
case kKryo:
RETURN_FUNC(memmove_func, memmove_kryo);
default:
RETURN_FUNC(memmove_func, memmove_a15);
}
RETURN_FUNC(memmove_func, memmove_a15);
}
typedef void* memcpy_func(void*, const void*, size_t);
@ -181,6 +163,26 @@ DEFINE_IFUNC(memcpy) {
return memmove_resolver();
}
typedef void* __memcpy_func(void*, const void*, size_t);
DEFINE_IFUNC(__memcpy) {
switch(get_cpu_variant()) {
case kCortexA7:
RETURN_FUNC(__memcpy_func, __memcpy_a7);
case kCortexA9:
RETURN_FUNC(__memcpy_func, __memcpy_a9);
case kKrait:
RETURN_FUNC(__memcpy_func, __memcpy_krait);
case kCortexA53:
RETURN_FUNC(__memcpy_func, __memcpy_a53);
case kCortexA55:
RETURN_FUNC(__memcpy_func, __memcpy_a55);
case kKryo:
RETURN_FUNC(__memcpy_func, __memcpy_kryo);
default:
RETURN_FUNC(__memcpy_func, __memcpy_a15);
}
}
typedef void* __memset_chk_func(void* s, int c, size_t n, size_t n2);
DEFINE_IFUNC(__memset_chk) {
switch(get_cpu_variant()) {
@ -193,8 +195,6 @@ DEFINE_IFUNC(__memset_chk) {
RETURN_FUNC(__memset_chk_func, __memset_chk_a9);
case kKrait:
RETURN_FUNC(__memset_chk_func, __memset_chk_krait);
case kDenver:
RETURN_FUNC(__memset_chk_func, __memset_chk_denver);
default:
RETURN_FUNC(__memset_chk_func, __memset_chk_a15);
}
@ -212,8 +212,6 @@ DEFINE_IFUNC(memset) {
RETURN_FUNC(memset_func, memset_a9);
case kKrait:
RETURN_FUNC(memset_func, memset_krait);
case kDenver:
RETURN_FUNC(memset_func, memset_denver);
default:
RETURN_FUNC(memset_func, memset_a15);
}
@ -242,8 +240,7 @@ DEFINE_IFUNC(__strcpy_chk) {
case kCortexA53:
RETURN_FUNC(__strcpy_chk_func, __strcpy_chk_a53);
case kCortexA55:
case kDenver:
RETURN_FUNC(__strcpy_chk_func, __strcpy_chk_denver);
RETURN_FUNC(__strcpy_chk_func, __strcpy_chk_a55);
default:
RETURN_FUNC(__strcpy_chk_func, __strcpy_chk_a15);
}
@ -282,8 +279,7 @@ DEFINE_IFUNC(__strcat_chk) {
case kCortexA53:
RETURN_FUNC(__strcat_chk_func, __strcat_chk_a53);
case kCortexA55:
case kDenver:
RETURN_FUNC(__strcat_chk_func, __strcat_chk_denver);
RETURN_FUNC(__strcat_chk_func, __strcat_chk_a55);
default:
RETURN_FUNC(__strcat_chk_func, __strcat_chk_a15);
}

32
libc/arch-arm/krait/bionic/memmove.S
View File

@ -1,32 +0,0 @@
/*
* Copyright (C) 2018 The Android Open Source Project
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#define MEMMOVE memmove_krait
#define MEMCPY __memcpy_krait
#include <arch-arm/denver/bionic/memmove.S>

32
libc/arch-arm/kryo/bionic/memmove.S
View File

@ -1,32 +0,0 @@
/*
* Copyright (C) 2018 The Android Open Source Project
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#define MEMMOVE memmove_kryo
#define MEMCPY __memcpy_kryo
#include <arch-arm/denver/bionic/memmove.S>